Silicon Nanophotonic Packaging
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Silicon Nanophotonic Packaging - overview<! -- ========================== PAGE CONTENT ========================== ->
A significant challenge to all silicon photonic platforms (IBM's or other) are cost efficient optical inputs and outputs (I/Os). By optical I/Os we mean the connections between the silicon photonic chip and optical wires connecting various photonic devices together. The cost of the optical connection to a silicon chip generally runs significantly higher than the cost of the silicon chip itself with challenges in optical bandwidth and port count scalability. To live up to the potential of silicon photonics, we believe a novel and disruptive strategy to optical inputs and outputs is required.
In the last few years, we have developed optical I/Os solutions aimed at low cost, wide optical bandwidth, and large optical port count. To bring the cost of optical I/Os down to the level of microelectronic I/Os, we believe we must leverage the existing fully-automated microelectronic packaging facilities for photonic packaging as we leverage microelectronics wafer production facilities for photonic wafer fabrication. This is in large contrast to the existing state of the art in optical I/Os which relies on high-cost specialized facilities with at best partial automation.
Main technical challenge
Generally, the most efficient of optical wires are the standard single-mode optical fibers that have been used in the telecom industry for decades. They can guide light for very long distances and with very low losses. Standard fibers benefit from a mature and standardized industry providing widespread infrastructure for fiber connections and quality assurance.
There are two main challenges in connecting standard single-mode optical fibers to nanophotonic chips:
- Large mismatch in energy confinement between optical fiber and nanophotonic waveguide.
- Tight alignment tolerances between optical fiber and nanophotonic waveguide.
The picture below illustrates the above challenges.
(1) The energy distribution in a standard single-mode fiber reaches a diameter of ~10 um. This must be compressed to a ~0.5 um energy distribution in a nanophotonic waveguide. We call this a mode transformation in photonics, which is similar to impedance matching in electronics.
(2) Typical microelectronic assembly tools have placement accuracy of +/- 10 um. This is well suited for the large solder bumps used for electric connections but highly insufficient for single-mode optics where 1-2 um alignment is needed.
(1) We address the mode mismatch between a fiber and a nanophotonic waveguide through adiabatic mode evolution. This type of mode transformation is fundamentally robust to manufacturing tolerances and offers much larger bandwidth than diffractive-based transformations such as vertical grating couplers.
(2) We address the large shortcomming in placement accuracy of microelectronic tools through precise self-alignment structures designed into the assembly.
This direction is demonstrated in the concepts illustrated above. Two approaches to fiber interfacing are shown: the parallelized fiber assembly and the compliant polymer interface. The preference of one approach over the other depends on application as both have different risks and rewards. On one hand, the fiber approach relies on mostly standard components with better known reliability and unsurpassed fiber optical transparency. On the other hand, the compliant polymer interface mechanically decouples the silicon chip from the optical connector resulting in improved thermo-mechanical cycling reliability over rigid connections such as direct fiber-to-chip attachment. Both fiber interfacing approaches are combined with solder self-aligned photonic flip-chip assembly to integrate the needed III-V light sources. In addition, all approaches are compatible with flip-chip electrical connections.
Our goal is the broad enablement of low-cost silicon photonic packaging. Please contact us if you would like to make use of any of the described technology. We will be updating this website regularly with exciting results as they can be made public.
Tymon Barwicz et al.
- Project Overview from 2016 (JSTQE 2016 overview paper, PDF)
- Project Overview from 2015 (Group IV Photonics 2015 plenary talk, slides in PDF)
- Parallelized fiber assembly results (Proceedings of ECTC 2015. PDF)
- Compliant interface optical performance (Proceedings of FiO 2016. PDF)
- Compliant interface self-alignment (Slides from Barwicz et al., ECTC 2014. PDF)
- Solder-aligned photonic flip-chip optical perfromance (Proceedings of FiO 2016. PDF)
- Solder-induced self-alignment yield (Proceedings of ECTC 2016. PDF)