Cooling 3D Chips     

Cooling 3D Chips - overview

Physics Accomplishment | 2008 - 2015

IBM researcher: TBD

Where the work was done: IBM T.J. Watson Research Center, IBM Zurich Research Lab

What we accomplished: A major problem in building 3D chips (with multiple layers of logic and memory stacked on top of each other) is how to cool the chip. Power that normally could be dissipated from the surface of the chip in a 2D design is now trapped in the interior, absent improvements and breakthroughs of the types noted below.

Related links:

• 2008 IBM Press Release on water-cooling 3D stacked chips.
• 2013 Article in Military and Aerospace Electronics on building cooling into 3D chips.
• 2015 Article in Military and Aerospace Electronics on further advances.

Image credit: c/net

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