OSMOSIS - Optical Shared MemOry Supercomputer Interconnect System - overview

Sept. 15, 2003. Corning Incorporated and IBM announced that they will team with the US Department of Energy and the National Nuclear Security Administration (NNSA) on a $20 million project to develop high-speed, optically switched interconnects for supercomputers.

The objective of this exploratory program is to accelerate the development of high speed optical technology and to demonstrate that optical interconnects can fulfill the requirements of high performance computing (HPC) systems in a cost-effective way. The deliverable of this 2.5-year contract is an all-optical switch prototype to interconnect future massively parallel HPC systems.

HPC switches must deliver low latency, low bit-error, high bandwidth, and scalability. This translates into the following specific requirements for our prototype demonstrator:

  • Latency: less than 1 us measured application–application
  • Bandwidth per port: 40 Gbit/s with 75% effective user bandwidth
  • Bit-error rate: 10-21
  • Minimum packet size: 64 - 256 Bytes,
  • Sustained throughput: > 95%,
  • Scalability: the system architecture must be designed to scale to at least 2048 nodes, and must be capable of scaling to higher line rates (at least 160 Gb/s),
  • Hw implementation: all electronic logic must be implemented using Field Programmable Gate Arrays (FPGA) for flexibility and to keep the cost of the demonstrator acceptable.

Our deliverables are the swicth arbiter and the control-path design for the input and output adapters. Corning is providing the optical switch based on SOA (Semiconductor Optical Amplifier) technology.


Step inside our OSMOSIS lab and take a look around