IBM FPgen Floating Point Test Generator (FPgen) - overview
A Deep-Knowledge Coverage-Driven Floating-Point Test Generator
FPgen is a test generation framework targeted toward verification of the floating-point datapath. FPgen is a generic tool that targets architectures that comply with the IEEE Standard 754-2008. In addition, it supports architectures that deviate from the standard.
FPgen provides a convenient platform for biasing and generating operand data for floating-point instructions.
Constraining the input operands of an operation is relatively straightforward. The main strength of FPgen lies in allowing more complex constraints, including:
- Constraints on the final result
- Constraints on the intermediate result(s)
- Constraints on relations between input operands
- Constraints on relations between inputs and results
- Simultaneous constraints on inputs and results
FPgen's ability to solve such complex constraints is based on a deep understanding of the floating-point semantics.
A floating-point verification plan is an important complement to FPgen's capabilities as a constraint solver. We constructed a generic test-plan (GTP) for floating-point to help verification engineers in the process of floating point unit (FPU) verification. This GTP is based on experience accumulated during the verification of multiple processors developed inside IBM as well as by external customers. The GTP is coverage oriented and comprises a large set of coverage models, each targeting a specific part of the FPU, or a particular feature of floating-point. These models are implemented as input files for FPgen to create biased-random test vectors to run in simulation.
We provide an IEEE compliant test suite that can be downloaded free of charge.