IBM Threadmill Post-Silicon Exerciser (Threadmill) Publications



2016

Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms
Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung{-}Boem Park, Wookyeong Jeong, Jae{-}Cheol Son
IEEE Design & Test , IEEE, 2016

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification
Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco
Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016, pp. 24:1--24:6

Using Graph-Based CSP to Solve the Address Translation Problem
Aharoni, Merav and Ben-Haim, Yael and Doron, Shai and Koyfman, Anatoly and Tsanko, Elena and Veksler, Michael
International Conference on Principles and Practice of Constraint Programming, pp. 843--858, 2016
Abstract


2015

Comparative study of test generation methods for simulation accelerators
Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung{-}Boem Park, Wookyeong Jeong, Jae{-}Cheol Son
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 321--324


2014

Verification of transactional memory in power8

... (DAC), 2014 51st ..., 2014 - ieeexplore.ieee.org

Effective post-silicon failure localization using dynamic program slicing
Ophir Friedler and Wisam Kadry and Arkadiy Morgenshtein and Amir Nahir and Vitali Sokhin
Proceedings of the conference on Design, Automation & Test in Europe, pp. 319, 2014


2013

Improving Utilization of Acceleration Platforms by Using Off-Platform Test Generation
Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Elena Tsanko
ChipEx, 2013

Post-Silicon Debugging of Transactional Memory Tests
Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin, Carla Ferreira and Joao Lourenco
Euro-TM Workshop on Transactional Memory (WTM 2013)


2012

Utilizing Acceleration Platforms Using Off-Platform Generated Test-Cases
Wisam Kadry, Dmitry Krestyashyn, Shimon Landa, Amir Nahir, Vitali Sokhin
49th Design Automation Conference, 2012

Architectural Coverage for Post-Silicon Exercisers
Nirmal M. Kumar, Varun Mallikarjunan, Subrat K. Panda, Amir Nahir, Vitali Sokhin, Avi Ziv
49th Design Automation Conference, 2012

Optimizing test-generation to the execution platform
A. Nahir, A. Ziv, S. Panda
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, pp. 304--309


2011

A unified methodology for pre-silicon verification and post-silicon validation
A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann
Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2011, pp. 1--6

Threadmill: A post-silicon exerciser for multi-threaded processors
A. Adir, M. Golubev, S. Landa, A. Nahir, G. Shurek, V. Sokhin, A. Ziv
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 860--865

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
A. Adir, A. Nahir, G. Shurek, A. Ziv, C. Meissner, J. Schumann
Proceedings of the 48th Design Automation Conference, pp. 569--574, 2011

Concurrent Generation of Concurrent Programs for Post-Silicon Validation
Allon Adir, Amir Nahir, Avi Ziv
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 31(8), 1297--1302, IEEE, 2011


2010

Reaching coverage closure in post-silicon validation
A Adir, A Nahir, A Ziv, C Meissner, J Schumann
Hardware and Software: Verification and Testing, 60--75, Springer, 2010

Bridging pre-silicon verification and post-silicon validation
A Nahir, A Ziv, M Abramovici, A Camilleri, R Galivanche, B Bentley, H Foster, A Hu, V Bertacco, S Kapoor
Design Automation Conference (DAC), 2010 47th ACM/IEEE, pp. 94--95