POWER7 (TM) Microprocessor Design       

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POWER7 (TM) Microprocessor Design Publications



2011


Multi-addressable register file
M K Gschwind, B Olsson
US Patent 7,877,582


2010



Method, system, and computer program product for path-correlated indirect address predictions
Richard J Eickemeyer, Michael K Gschwind, Ravi Nair, Robert A Philhower
US Patent 7,797,521


Alignment of cache fetch return data relative to a thread
M K Gschwind, H M Jacobson, R A Philhower
US Patent 7,725,659


2009

Soft error handling in microprocessors
Michael Karl Gschwind, Robert Philhower
US Patent 7,512,772

IMPLEMENTING INSTRUCTION SET ARCHITECTURES WITH NON-CONTIGUOUS REGISTER FILE SPECIFIERS
M K Gschwind, R K Montoye, B Olsson, J Wellman
US Patent App. 12/534,968



2008

Optimized Scalar Promotion with Load and Splat SIMD Instructions
A E Eichenberger, M K Gschwind, J A Gunnels
US Patent App. 20,090/307,656



2007


DESIGN STRUCTURE FOR PREDICTIVE DECODING
B Blaner, M K Gschwind
US Patent App. 20,090/119,494

METHOD AND APPARATUS FOR PREDICTIVE DECODING
B Blaner, M K Gschwind
US Patent App. 11/743,699



2006