Reliability and Power-Aware Microarchitectures       

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Ramon  Bertran Monfort photo Pradip Bose photo Alper Buyuktosunoglu photoCHIA-YU CHEN photo photo Karthik V. Swaminathan photo

Reliability and Power-Aware Microarchitectures Publications



2017

A Low Voltage RISC-V Heterogeneous System
Eldridge, Schuyler and Swaminathan, Karthik and Chandramoorthy, Nandhini and Buyuktosunoglu, Alper and Roelke, Alec and Verma, Vaibhav and Joshi, Rajiv and Stan, Mircea and Bose, Pradip
First Workshop on Computer Architecture Research with RISC-V (CARRV), 2017
Abstract

MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA
Eldridge, Schuyler and Bertran, Ramon and Buyuktosunoglu, Alper and Bose, Pradip
7th RISC-V Workshop, 2017
Abstract   Video

BRAVO: Balanced Reliability-Aware Voltage Optimization
K. Swaminathan, N. Chandramoorthy, C. Cher, R. Bertran, A. Buyuktosunoglu, P. Bose
International Symposium on High-Performance Computer Architecture (HPCA), 2017

SHIVA: An Integrated Toolset for Cross-Layer Modeling in Support of Resilient, Low-Power Embedded Processor Design
Karthik Swaminathan, Ramon Bertran, Schuyler Eldridge, Chen - Yong Cher, Hans Jacobson, Augusto Vega, Alper Buyuktosunoglu, John - David Wellman, Robert Montoye, Pradip Bose
GOMACTech-17, 2017

Power Supply Noise in a 22nm z13TM Microprocessor
P. I. Chuang, C. Vezyrtzis, D. Pathak, R. Rizzolo, T. Webel, T. Strach, O. Torreiter, P. Lobo, A. Buyuktosunoglu, R. Bertran, M. Floyd, M. Ware, G. Salem, S. Carey, P. Restle
2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 438-439


2016

HIERARCHICAL IN-MEMORY SORT ENGINE
Buyuktosunoglu, Alper and Chellappa, Srivatsan and Kirihata, Toshiaki and Swaminathan, Karthik V
US Patent 20,160,085,702

GENERATION AND APPLICATION OF STRESSMARKS IN A COMPUTER SYSTEM
Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu, Timothy J Slegel
US Patent 20,160,110,276

Cycle-level thread alignment on multi-threaded processors
Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu, Timothy J Siegel
US Patent 9,507,646

PROCESSOR STRESSMARKS GENERATION
Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu
US Patent 20,160,110,278


2015


ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,082,070

EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,077,170

A Case for Approximate Computing in Real-Time Mobile Cognition
K. Swaminathan, C. Lin, A. Vega, A. Buyuktosunoglu, P. Bose, S. Pankanti.
Workshop on Approximate Computing (WACAS), in conjunction with ASPLOS 2015

Robust power management in the IBM z13
T. Webel, P.M. Lobo, R. Bertran, G.M. Salem, M. Allen-Ware, R. Rizzolo, S.M. Carey, T. Strach, A. Buyuktosunoglu, C. Lefurgy, P. Bose, R. Nigaglioni, T. Slegel, M.S. Floyd, B.W. Curran
IBM Journal of Research and Development 59(4), 16--16, 2015

Resilient, UAV-Embedded Real-Time Computing
A. Vega, C. Lin, K. Swaminathan, A. Buyuktosunoglu, S. Pankanti, P. Bose
International Conference on Computer Design (ICCD), Oct 2015

Resilient Mobile Cognition: Algorithms, Innovations, and Architectures
R. Viguier, C. Lin, K. Swaminathan, A. Vega, A. Buyuktosunoglu, S. Pankanti, P. Bose, H. Akbarpour, F. Bunyak, K. Palaniappan, G. Seetharaman.
International Conference on Computer Design (ICCD), Oct 2015.

Safe Limits on Voltage Reduction Efficiency in GPUs: a Direct Measurement Approach
Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran, Pradip Bose, Vijay Janapa Reddi
MICRO '15: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (Acceptance Ratio: ??. Conf. Rank: A), pp. 0--0, IEEE Computer Society, 2015

HIERARCHICAL IN-MEMORY SORT ENGINE
Buyuktosunoglu, Alper and Chellappa, Srivatsan and Kirihata, Toshiaki and Swaminathan, Karthik V
US Patent 20,150,347,592

Optimization of Application Workflow in Mobile Embedded Devices
Pradip Bose, Liang Wang, Augusto Vega, Alper Buyuktosunoglu, Hans Jacobson, Ramon Bertran, Chen-Yong Cher, William J Song, Karthik Swaminathan


2014

Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits
Pradip Bose, Alper Buyuktosunoglu, John A Darringer, Moinuddin K Qureshi, Jeonghee Shin
US Patent 8,683,418


Characterization of Transient Error Tolerance for a Class of Mobile Embedded Applications
Liang Wang, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose, Kevin Skadron
2014 IEEE International Symposium on Workload Characterization, IISWC 2014, Raleigh, NC, USA, October 26-28, 2014

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities
Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose, Timothy J Slegel, Gerard Salem, Sean Carey, Richard F Rizzolo, Thomas Strach
Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on, pp. 368--380

Energy Characterization Methodologies for CMP SMT Processors Systems
Ramon Bertran
PhD Thesis Computer Architecture Department, UPC, Campus Nord UPC, D6 Building / C6 Building, Jordi Girona 1-3, 08034 Barcelona, December 2014



2013

Processor with memory-embedded pipeline for table-driven computation
Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C Hunter, Jude A Rivers, Vijayalakshmi Srinivasan
US Patent App. 14/053,978

Dynamic hard error detection
Pradip Bose, Alan Gara, Hans M Jacobson
US Patent App. 13/765,320

SMT switch: Software Mechanisms for Power Shifting
Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose
Computer Architecture Letters 12(2), 67--70, IEEE, 2013

Measuring data switching activity in a microprocessor
Pradip Bose, Alper Buyuktosunoglu, Christopher J Gonzalez, Moinuddin K Qureshi, Victor Zyuban
US Patent 8,458,501


Power management for a computer system
Pradip Bose, Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/837,655


2012

Thread consolidation in processor cores
Pradip Bose, Alper Buyuktosunoglu, Bryan S Rosenburg, Kyung D Ryu, Augusto J Vega
US Patent App. 13/681,497

Dynamic power distribution
Pradip Bose, Alper Buyuktosunoglu, Hans M Jacobson
US Patent App. 13/685,912

Managing instructions for more efficient load/store unit usage
Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, Dung Quoc Nguyen, Bruce Joseph Ronchetti
US Patent 8,271,765

Modeling system-level effects of soft errors
Pradip Bose, Prabhakar N Kudva, Jude A Rivers, Pia N Sanda, John-David Wellman
US Patent 8,091,050


2011

Local Computation Logic Embedded in a Register File to Accelerate Programs
Pradip Bose, Alper Buyuktosunoglu, Jeffrey Haskell Derby, Michele Martino Franceschini, Robert Kevin Montoye, Augusto J Vega
US Patent App. 13/211,701

Hardware Execution Driven Application Level Derating Calculation for Soft Error Rate Analysis
Pradip Bose, Meeta S Gupta, Prabhakar N Kudva, Daniel A Prener
US Patent App. 13/271,827




2010

LOW OVERHEAD DYNAMIC THERMAL MANAGEMENT IN MANY-CORE CLUSTER ARCHITECTURE
Eren Kursun, Philip G. Emma, Pradip Bose, Jude A Rivers
US Patent App. 12/698,545


2009

Performance optimizations for distributed real-time text indexing
Ankur Narang, Karthik Swaminathan, Prashant Agrawal
High Performance Computing (HiPC), 2009 International Conference on, pp. 398--407




TEMPERATURE-CONTROLLED 3-DIMENSIONAL BUS PLACEMENT
Eren Kursun, Philip G. Emma, Jude A Rivers
US Patent App. 12/493,599


Reliability challenges and system performance at the architecture level
J A Rivers, P Kudva
Design \& Test of Computers, IEEE 26(6), 62--73, IEEE, 2009


2008



Lifetime Reliability Awareness for Microprocessors
J Srinivasan, S V Adve, P Bose, J A Rivers
2008 - Citeseer, Citeseer

Predicting microprocessor lifetime reliability using architecture-level structure-aware techniques
Pradip Bose, Zhigang Hu, Jude A Rivers, Jeonghee Shin, Victor Zyuban
US Patent App. 12/189,416

Phaser: Phased methodology for modeling the system-level effects of soft errors
JA Rivers, P Bose, P Kudva, J D Wellman, PN Sanda, EH Cannon, LC Alves
IBM Journal of Research and Development 52(3), 293--306, IBM, 2008


2007

METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME
P Bose, Z Hu, J A Rivers, J Shin, V Zyuban
US Patent App. 20,080/256,383

Reliability morph for a dual-core transaction-processing system
Pradip Bose, Philip George Emma, Jude A Rivers, Sumedh Wasudeo Sathaye
US Patent App. 11/684,987


2005

The case for microarchitectural awareness of lifetime reliability
Jayanth Srinivasan, Sarita V Adve, Pradip Bose, Jude Rivers, Y Li, D Brooks, Z Hu, K Skadron, V Srinivasan, M Gschwind, others
IEEE Micro 25(3), 70--80, 2005

Exploiting structural duplication for lifetime reliability enhancement
J Srinivasan, S V Adve, P Bose, J A Rivers
ACM SIGARCH Computer Architecture News 33(2), 520--531, ACM, 2005

Lifetime reliability: Toward an architectural solution
J Srinivasan, S V Adve, P Bose, J A Rivers
IEEE Micro 25(3), 70--80, 2005


2004

The case for lifetime reliability-aware microprocessors
J Srinivasan, S V Adve, P Bose, J A Rivers
2004 - computer.org, Published by the IEEE Computer Society

The Impact of Technology Scaling on Lifetime Reliability (PDF)
J Srinivasan, S V Adve, P Bose, J A Rivers
2004 - computer.org, Published by the IEEE Computer Society


2003

Ramp: A model for reliability aware microprocessor design
J Srinivasan, S V Adve, P Bose, J Rivers, C K Hu
IBM Research Report, Citeseer, 2003


2000

Performance and functional verification of microprocessors
P Bose, J A Abraham
VLSI Design, 2000, pp. 58--63


1999


Validation of Turandot, a fast processor model for microarchitecture exploration
M Moudgill, P Bose, J H Moreno
Performance, Computing and Communications Conference, 1999, pp. 451--457

Challenges in processor modeling and validation
P Bose, T M Conte, T M Austin
IEEE Micro 19(3), 9--14, 1999


1998

Performance test case generation for microprocessors
P Bose
VLSI Test Symposium, 1998, pp. 54--59


Year Unknown

VSR Sort: A Novel Vectorised Sorting Algorithm and Architecture Extensions for Future
Victor Jimenez, Alper Buyuktosunoglu, Pradip Bose, Supercomputing Center, Mateo Valero, Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip B Gibbons, others
ieeexplore.ieee.org, 0

A Case for Energy-Aware Accounting in Large-Scale Computing Facilities
Cost Metrics, V\ictor Jim\'enez, Francisco J Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero
..., E Kursun, C Isci, A Buyuktosunoglu, P Bose..., 0

Complexity-Effective Design
Pradip Bose, David H Albonesi, Diana Marculescu
ece.rochester.edu, 0

The Case for Lifetime Reliability-Aware Microprocessors Ѓ
J Srinivasan, S V Adve, P Bose, J A Rivers
ece.northwestern.edu, 0

Balancing new reliability challenges and system performance at\&\# xD; the architecture level
P Kudva, J Rivers
Design \& Test of Computers, IEEE pp. 99, 1, IEEE, 0