Computer Architecture     


Computer Architecture - Patents

The following patents are issued since 2010 in Computer Architecture and related areas.

  • Method and System for Multiprocessor Emulation on a Multiprocessor Host System, 11/30/2010, US patent 7844446, John O'Brien, Kathryn O'Brien, Erik Altman, Daniel Prener, Peter H Oden, Ravi Nair, Sumedh Sathaye
  • Method and apparatus for application-specific dynamic cache placement, 11/16/2010, US Patent 7836256, Krishnan Kailas, Rajiv Ravindran, Zehra Sura.
  • Architectural Level Throughput Based Power Modeling Methodology And Apparatus For Pervasively Clock-Gated Processor Cores, 10/19/2010, US patent7818696, Pradip Bose, Malcolm Ware, Srinivasan Ramani, Ken Vu.
  • Processor Bus For Performance Monitoring With Digests, 10/19/2010, US patent 7818624, Ravi Nair, Hillery Hunter.
  • Digital Measuring System And Method For Integrated Circuit Chip Operating Parameters, 10/12/2010, US patent 7813815, Rick Rand, Philip Emma, Herschel Ainspan, Arthur Zingher.
  • DRAM Cache With On-Demand Reload, 9/28/2010, US patent 7805658, Wing Kin Luk, Ravi Nair.
  • Method For Constructing Autonomic Advisors And Learning Procedural Knowledge From Scored Examples, 9/21/2010, US patent 7801835, Daniel Oblinger, Lawrence Bergman, Tessa Lau, Vittorio Castelli, Prabhakar Kudva.
  • Method, System, And Computer Program Product For Path-Corrrelated Indirect Addres Predictions, 9/14/2010, US patent 7797521, Richard Eickemeyer, Robert Philhower, Ravi Nair, Michael Gschwind.
  • Implementing Instruction Set Architectures With Non-Contiguous Register File Specifiers, 9/7/2010, US patent 7793081, Brett Olsson, John David Wellman, Robert Montoye, Michael Gschwind.
  • Compiler Implemented Software Cache Method In Which Non Aliased Explicity Fetched Data Are Excluded, 8/24/2010, US patent 7784037, John O'Brien, Kathryn O'Brien, Zehra Sura, Byoungro So, TONG CHEN, Tao Zhang.
  • Method And Apparatus For Preventing Soft Error Accumulation In Register Arrays, 8/10/2010, US patent 7774654, Balaram Sinharoy, Pradip Bose, Victor Zyuban, Jude Rivers.
  • Performing Useful Computations While Waiting For A Line In A System With A Software Implemented Cache, 7/27/2010, US patent 7765360, John O'Brien, Kathryn O'Brien.
  • Bounded Starvation Checking Of An Arbiter Using Formal Verification, 7/6/2010, US patent 7752369, Brian Monwai, Krishnan Kailas, Viresh Paruthi.
  • State Machine Based Filtering Of Non-Dominant Branches To Use A Modified Gshare Scheme, 6/29/2010, US patent 7747845, Brian Prasky, Moinuddin Qureshi.
  • Efficient Generation Of Simd Code In Presence Of Multi-Threading And Other False Sharing Conditions And In Machines Having Memory Protection Support, 6/1/2010, US patent 7730463, Peng Zhao, KAI-TING WANG, Alexandre Eichenberger, Peng Wu.
  • Compact Representation Of Instruction Execution Path History, 5/25/2010, US patent 7725692,Ravi Nair.
  • Alignment Of Cache Fetch Return Data Relative To A Thread, 5/25/2010, US patent 7725659, Hans Jacobson, Robert Philhower, Michael Gschwind.
  • Three Dimensional Integrated Circuit And Method Of Design, 5/25/2010, US patent 7723207, David Kung, Kathryn Guarini, Mark Lavin, Meikei Ieong, Syed M Alam, Ibrahim Elfadel, Prabhakar Kudva.
  • Method For The Asynchronous Arbitration Of A High Frequency Bus In A Long Latency Environment, 5/25/2010, US patent 7724759, Ferenc Bozso, Sampath Purushothaman, Satya Nitta, Philip Emma, Bruce Furman.
  • System, Method And Computer Program Product For Executing A Cache Replacement Algorithm, 5/4/2010, US patent 7711904, Thomas Puzak, Daniel N Lynch, Philip Emma.
  • Method And System For Tracking Instruction Dependency In An Out Of Order Processor, 5/4/2010, US patent 7711929, William Burky, Krishnan Kailas.
  • System And Method For Predicting A Hardware And/Or Software Metrics In A Computer System Using Models, 4/13/2010, US patent 7698249, Alper Buyuktosunoglu, Ruhi Sarikaya.
  • 3-Dimensional Integrated Circuit Architecture, Structure And Method For Fabrication Thereof, 4/6/2010, US patent 7692944, Philip Emma, Paul Coteus, Kerry Bernstein.
  • Interlocked Synchronous Pipeline Clock Gating, 3/23/2010, US patent 7685457, Peter W Cook, Pradip Bose, Hans Jacobson, Stanley E Schuster, Prabhakar Kudva.
  • Structure Comprising 3-Dimensional Integrated Circuit Architecture Circuit Structure, And Instructions For Fabrication Thereof, 3/23/2010, US patent 7684224, Philip Emma, Paul Coteus, Kerry Bernstein.
  • Logic Block Timing Estimation Using Conesize, 3/9/2010, US patent 7676779, Mark Mayo, Reinaldo A Bergamaschi, Sean Carey, Matthew E Mariani, Ruchir Puri, Brian Curran, Prabhakar Kudva.
  • Effective Delayed, Minimized Switching, Btb Write Via Recent Entry Queue That Has The Ability To Delay Decode, 3/9/2010, US patent 7676663, Thomas Puzak, Brian Prasky, Allan Hartstein.
  • Method And System For Versioning Codes Based On Relative Alignment For Single Instruction Multiple Data Units, 3/2/2010, US patent 7673284, Peng Zhao, KAI-TING WANG, Alexandre Eichenberger, Peng Wu.
  • Method And Apparatus For A Computing System Using Meta Program Presentation, 2/16/2010, US patent 7665070,Krishnan Kailas
  • High Speed Data Channel Including A Cmos Vcsel Driver And A High Performance Photodetector And A Cmos Photoreceiver, 2/9/2010, US patent 7659535, Ferenc Bozso, Philip Emma.
  • Method And System For Dependency Tracking And Flush Recovery For An Out Of Order Microprocessor, 2/9/2010, US patent 7660971, Balaram Sinharoy, Vikas Agarwal, William Burky, Krishnan Kailas.
  • Context Look Ahead Storage Structures, 2/2/2010, US patent 7657726, Thomas Puzak, Philip Emma, Vijayalakshmi Srinivasan, Brian Prasky, Moinuddin Qureshi, Allan Hartstein.
  • Error Correcting Logic System, 1/5/2010, US patent 7642813, Paul Kartschoke, Norman Rohrer, Philip Emma, John Fifield, Kerry Bernstein, Bill Klaasen.

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Upcoming Seminars

  • November 4, 2010
    Architecture, Design, and Implementation of a 3D-IC Many-core Processor, Prof. Hsien-Hsin S. Lee, Georgia Institute of Technology.
  • November 5, 2010
    Understanding the memory systems of a modern NUMA Processor, Prof. Thomas Gross, ETH Zurich.

A complete list of recent seminars can be found here.