eLite DSP Project - Methodology

Codesign methodology

The co-design and evaluation methodology deployed in the development of the eLite architecture has been built around the interaction between the multiple dimensions of the problem. The process has been iterative, including several cycles in which the architecture was evaluated in each dimension (i.e., performance, code size, hardware complexity, power consumption, etc.). At the center of the interacting components (see the figure below) lies a description of the architecture, represented by the "Instruction Set Architecture (ISA) database," which reflects the view of the architecture at a given point in time. The processes by which these components are exercised is also illustrated in the figure. The "Exploration" path is characterized by a fast turnaround time, wherein the focus of the evaluation is on instruction-set architecture performance measures and estimates of power/performance trade-offs. The "Evaluation" path is characterized by longer turnaround time but includes detailed analysis from hardware design and implementation. As their names imply, each path has a well-defined objective. The exploration path is used to evaluate proposed features and changes, by modifying the different components of the environment as necessary and by performing cycle-accurate simulation, although the simulation does not include all the details of the implementation. In contrast, the evaluation path focuses on providing accurate performance and power consumption metrics, as obtained from detailed description of the hardware elements in an implementation.

The eLite architecture has been developed following a power/performance metric through a set of benchmarks. This set was chosen according to the following three criteria:

  • relevance to the target applications, mainly wireless and line communication, voice applications, and media applications;
  • moderate size functions; and
  • coverage of the various units as well as system issues such as interrupts.

The set of benchmarks chosen includes simple and very common functions such as FIR filters, IIR filters, vector add, vector max, control code, etc. The benchmarks suite also includes more complex functions such as FFT, Interpolator and decimator, 2D-IDCT, and Viterbi decoder, among others. An instruction-set simulator was used for each version of the architecture to analyze the performance. Conclusions were made about areas in which improvements to the architecture were needed. The decision on which solution should be adopted for a particular issue was made according to the power / performance metric, while trying to maximize performance. This process was repeated for each version of the architecture, leading to significant performance improvement each time while maintaining modest rise in power consumption and silicon area. In addition, based on the performance of each kernel in the relevant field (voice, audio, communication, video, etc.), key applications have been studied in order to evaluate the expected performance of entire applications. The evaluation of each application included aspects such as cycle count, code size, memory requirements, etc.

The final design of the eLite architecture shows that it provides similar or better performance (in cycle count) than state-of-the-art digital signal processors in key areas while maintaining lower power consumption and higher frequency of operation. The power/performance capabilities provided by the eLite architecture is the result of the co-design effort, and corresponds to one of the key features offered by this design.