Threadmill - DAC2012 Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-Practices
Manager, Post-Silicon Validation & Design Automation, IBM Research Lab in Haifa.
Threadmill Post-Silicon Exerciser Team Lead, Post-Silicon Validation & Design Automation Group, IBM Research Lab in Haifa.
Chief Engineer Power Systems Bring Up, IBM Corp., Austin, TX.
Professor Subhasish Mitra
Departments of Electrical Engineering and Computer Science, Stanford University., Stanford, CA.
David S. Erikson
Sr. MTS engineer in AMD's Silicon Validation Architecture team, Advanced Micro Devices, Fort Collins, CO.
Dr. Brad Quinton
Chief Architect for the Embedded Instrumentation Group at Tektronix, Tektronix, Inc., Vancouver, BC, Canada.
Professor Alan J. Hu
Department of Computer Science University of British Columbia, Vancouver, BC, Canada.
Intel Fellow in the Intel Architecture Group, Platform Validation Engineering, Intel Corp., Portland, OR.
Principal Engineer in the Platform Validation Engineering dep, Intel Corp., Santa Clara, CA.
Professor Valeria Bertacco
Department of Electrical Engineering and Computer Science. University of Michigan, Ann Arbor, MI.
Manager, SoC post silicon validation and emulation, Freescale Semiconductor, Inc., Noida, India.
Chief Scientist for Verification, Mentor Graphics Corp., Plano, TX.