Energy Secure Systems Architecture - Bibliography

Paper references (a representative set of 20) for talks given by Pradip Bose and Alper Buyuktosunoglu

(A full, comprehensive list of paper references covering all the talks will be provided to attendees as part of the Tutorial Notes)

  1. P. Bose, A. Buyuktosunoglu, C-Y. Cher, J. A. Darringer, M. S. Gupta, H. Hamann, H. Jacobson, P. N. Kudva, E. Kursun, N. Madan, I. Nair, J. A. Rivers, J. Shin, A. J. Weger, V. Zyuban, “Power-efficient, reliable microprocessor architectures: modeling and design methods,” Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.
  2. N.Madan, A. Buyuktosunoglu, P. Bose, M. Annavaram, "A case for guarded power gating in multi-core processors", Proc. 17th Int’l. Symp. on High-Performance Comp. Arch. (HPCA), February 2011
  3. D. Brooks and M. Martonosi, “Dynamic thermal management for high-performance microprocessors,” Proc. 7th Int’l. Symp. on High-Performance Comp. Arch. (HPCA), 2001.
  4. M. Floyd, M. Ware, K. Rajamani, B. Brock, C. Lefurgy, A. Drake, L. Pesantez, T. Gloekler, J. Tierno, P. Bose, A. Buyuktosunoglu, Introducing the Adaptive Energy Management Features of the POWER7 chip" IEEE MICRO, March 2011.
  5. P. Kocher, R. B. Lee, G. McGraw, A. Ranganathan, S. Ravi, “Security as a new dimension in Embedded System Design”, Proc. of 41st. Design Automation Conference (DAC), June 2004; also, Ruby Lee, “Processor Architectures for Efficient Secure Information Processing, 41st. Design Automation Conference invited talks, June 2004.
  6. M.K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, B. Abali, "Enhancing Lifetime and Security of Phase Change Memories via Start-Gap Wear Leveling", Proc. of Int'l Symposium on Microarchitecture (MICRO), December 2009.
  7. J. Srinivasan, S. A. Adve, P. Bose and J. Rivers, "Lifetime Reliability: Toward an Architectural Solution," IEEE Micro, special issue on Emerging Trends, vol. 25, issue 3, May-June 2005, pp. 2-12.
  8. Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston, “A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. 353-362,” Proc. Int’l. Symp. on Computer Architecture (ISCA), June 2008.
  9. R. Joseph, D. Brooks and M. Martonosi, “Control techniques to eliminate voltage emergencies in high performance processors,” Proc. Int’l. Symp. on High Performance Comp. Arch. (HPCA), Feb. 2004.
  10. B. Black, M. Annavaram, N. Brekelbaum, J. Devale, L.Jiang, G. H. Loh, D. Mccauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb, "Die Stacking (3D) Microarchitecture", Proc. of 39th Int'l Symposium on Microarchitecture (MICRO), December 2006
  11. A. Lungu, P. Bose, D. Sorin, S. German and G. Janssen. "Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification." Proc. 7th ACM-IEEE Int’l. Conference on Formal Methods and Models for Codesign (MEMOCODE), July 2009.
  12. D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran, S.K.S. Hari, D. Sorin, A. Meixner, A. Biswas, and X. Vera. "Architectures for Online Error Detection and Recovery in Multicore Processors." To appear in Design, Automation & Test in Europe (DATE), March 2011.
  13. Anita Lungu and Daniel J. Sorin. "Verification-Aware Microprocessor Design." Proc. 16th Int’l. Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
  14. D.H. Albonesi, R. Balasubramonian, S.G. Dropsho, S. Dwarkadas, E.G. Friedman, M.C. Huang, V. Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook, and S.E. Schuster. "Dynamically Tuning Processor Resources with Adaptive Processing." IEEE Computer, Special Issue on Power-Aware Computing, Vol. 36, No. 12, pp. 49-58, December 2003.
  15. Z. Wu, M. Xie and H. Hwang, Energy attack on server systems. Proc. 5th USENIX Workshop on Offensive Technologies (WOOT), 2011.
  16. S. Govindavajhala and A. W. Appel, “Using memory errors to attack a virtual machine,” IEEE Symp. on Security and Privacy, May 2003.
  17. P. Dadvar and K. Skadron, “Potential thermal security risks in,” 21st IEEE Semi-Therm Symp., 2005.
  18. P. Bose, A. Buyuktosunoglu, J. A. Darringer, M. S. Gupta, M. B. Healy, H. Jacobson, I. Nair, J. A. Rivers, J. Shin, A. Vega, A. J. Weger, “Power management of multi-core chips: challenges and pitfalls,” Proc. Design Automation and Test in Europe (DATE), March 2012.
  19. S. Sethumadhavan et al. Tutorial on Hardware Security, ISCA 2011.
  20. M. Floyd, M. Ware, K. Rajamani, T. Gloekler, B. Brock, P. Bose, A. Buyuktosunoglu, J. Rubio, B. Schubert, B. Spruth, J. Tierno, L. Pesantez. Adaptive Energy Management Features of the IBM POWER7 Chip. IBM Journal of Research and Development, Vol. 55, May/June 2011.