Energy Secure Systems Architecture - Speakers

Confirmed Invited Speakers (in alphabetical order of last name):


"Low Power and Security Trade-off in Hardware: From True Random Number Generators to DPA Resilience"

Antonio Acosta-Jimenez (University of Seville)


Abstract: Nowadays, security is smoothly moving to hardware domain, where cryptocircuits must ensure the secure operation of the whole system. In portable devices, the security and low power consumption are mutually required issues, making necessary both the reduction in power consumption of secure cryptocircuits and enforcing security capabilities of low power solutions. In this speech, the reduction in power consumption of hardware solutions without security degradation are analyzed through examples going from True Random Number Generators based on Physical Unclonable Functions up to DPA resistant cryptocircuits.

Bio: Antonio Jose Acosta-Jimenez received the B.Sc. degree in 1989, the M.Sc. degree in 1991 and the Ph.D. degree in 1995 in Electronic Physics, from the University of Seville, Spain. He is Full Professor at the Department of Electronics and Electromagnetism, University of Seville, since 2011. He is also Senior Researcher at the Institute of Microelectronics of Seville, CNM-CSIC.
His current research interests are in the areas of CMOS digital VLSI design, low power and low noise mixed-signal circuits, description of timing phenomena in VLSI digital system, asynchronous and self-timed circuits and cryptographic VLSI circuits. He has coauthored more than one hundred international publications, supervised 4 PhD Thesis, and leaded national and European R+D Projects in the above mentioned areas. He serves as Associate Editor in Integration, The VLSI Journal, International Journal on Circuit Theory and Applications and Journal of Low Power Electronics. He was General Co-chair of 2002 PATMOS Workshop.



"PowerAPI: A Comprehensive Interface for Power/Energy Measurement and Control for Extreme Scale Computing"

Ryan Grant (Sandia National Laboratories)


Abstract: This talk will present a Power API currently being developed at Sandia National Laboratories for use in next generation supercomputers. With community support and input, it is being designed to provide a single interface to multiple different potential actors on system power. To address these requirements, application/OS and HW interfaces are included, as well as higher level monitoring and control and accounting interfaces. This API design is flexible enough to support hardware vendor as well as system integrator provided power management features. It will provide a single common API for the development of power management requirements from the facilities manager level down to the operating system and hardware interaction level.
This talk will focus on the API design for allowing applications and users to interface with hardware power management solutions on large-scale multi-node multi-core capability-class supercomputers. It will discuss the system model being used, as well as methods of managing real-world power capping for Exascale-class systems. Use case examples will be provided to demonstrate the utility of the interface in a variety of scenarios.
The talk will conclude with a description of the ideas being proposed for providing security for this interface. This early stage, work-in-progress overview is intended to engage the power-security community and lead to constructive discussions on our current approach and emerging novel ideas on power-security.

Bio: Dr. Ryan Grant works as a Postdoctoral Appointee in the Scalable Systems Software Department at Sandia National Laboratories with Ron Brightwell. His current research concerns power efficiency for capability class systems and next-generation interconnect technologies. He works as a member of the PowerAPI specification group as well the Portals networking specification committee. He serves on the Message Passing Interface (MPI) Forum and is a developer for Open MPI.
Ryan received his PhD in 2012 from Queen’s University in Kingston, Ontario, Canada, where he was an Alexander Graham Bell Graduate Scholar. He won several awards for his Doctoral research and teaching activities throughout his studies. He currently has more than 20 published/accepted publications in the areas of energy efficiency and networking.




"Hardware and Software Cooperative Sleep-Mode Control for Fine-Grained Power-Gating in Embedded Microprocessors"

Masaaki Kondo (University of Tokyo)


Abstract: Power-performance efficiency is still remaining a primary concern in designing LSI chips. One of the sources of today's power inefficiency for LSI chips is leakage power. Fine-grained power-gating is recently emerged as a technique to minimize leakage current during the active processor cycles by switching on and off a logic blocks in much finer temporal/spatial granularity. Energy overhead associated with frequent sleep mode transition, however, is a issue to be addressed, leading to the necessity of smart power management schemes. In this talk, I will introduce an architecture and compiler cooperative fine-grained power-gating technique which ensure the robustness against negative power reduction caused by the energy overhead. The detailed evaluation of fine-grained run-time power-gating for microprocessors' functional units using a fabricated embedded microprocessor called Geyser-3 will also be presented.

Bio: Masaaki Kondo is an associate professor in the Graduate School of Information Science and Technology at the University of Tokyo. He received the B.E. degree in College of Information Sciences and the M.E degree in Doctoral Program in Engineering from University of Tsukuba, and the Ph.D. degree in Graduate School of Engineering from the University of Tokyo. His research interests include computer architecture, high performance computing, VLSI design, and embedded systems, with focusing on low-power and high-performance microprocessor design, power management for high performance cluster systems, and dependable cluster systems. He has engaged in many research projects as PI/Co-PI with research grants administrated by Japanese government (MEXT, JSPS, JST, and NEDO) and industry.


"Design of Efficient and Trustworthy On-Chip Power Delivery Systems"

Selcuk Kose (University of South Florida)


Abstract: The power efficiency and trustworthiness of an integrated circuit depend strongly on the power delivery system. The proliferation of ultra-small on-chip voltage regulators enables new circuit topologies and control techniques that concurrently increase power conversion efficiency and minimize information leakage through side-channels.
The presentation will focus on reviewing the recent advancements in on-chip power delivery and investigating possible opportunities to exploit on-chip voltage converters as a countermeasure against power analysis side-channel attacks. A recently developed power-efficient switched capacitor (SC) voltage converter will be introduced. The individual stages within this SC voltage converter are adaptively turned on and turned off based on the workload to maintain high power conversion efficiency over a wide load current range. In the second portion of the presentation, the proposed SC voltage converter system is utilized to scramble the input power consumption profile of an integrated circuit. Two new voltage converter control techniques: i) converter-gating and ii) converter-reshuffling will be explained with simulation results. Converter-gating is used to turn on and turn off individual stages of an interleaved SC voltage converter when the load current changes. Converter-reshuffling is used to juggle the active converter stages with inactive stages. These two techniques generate random spikes in the input current profile and insert delay uncertainty to the existing current spikes, making the analysis of the power consumption profile significantly difficult. These circuits and control techniques will fundamentally change the manner in which power is delivered in cryptographic circuits, concurrently satisfying high power efficiency and trustworthiness.

Bio: Selcuk Kose received the B.S. degree in electrical and electronics engineering from Bilkent University, Ankara, Turkey, in 2006, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, New York, in 2008 and 2012, respectively. He is currently an Assistant Professor with the Department of Electrical Engineering, University of South Florida, Tampa, Florida. He previously worked at the Scientific and Technological Research Council (TUBITAK), Ankara, Turkey, the Central Technology and Special Circuits Team in the enterprise microprocessor division of Intel Corporation, Santa Clara, California, and the RF, Analog, and Sensor Group, Freescale Semiconductor, Tempe, Arizona. His current research interests include the analysis and design of high performance integrated circuits, on-chip DC-DC converters, and interconnect related issues with specific emphasis on the design, analysis, and management of on-chip power delivery networks, 3-D integration, and hardware security.
Dr. Kose received the National Science Foundation CAREER award in 2014. He is currently serving in the editorial boards of the Journal of Circuits, Systems, and Computers and Microelectronics Journal. He is a member of the technical program committee of a number of conferences.



"Economic Mechanisms for Managing Risk in Heterogeneous Datacenters"

Benjamin Lee (Duke University)


Abstract: As cloud computing proliferates, demand for datacenter computing capacity increases. Moreover, we must increase capacity within today's megawatt-scale power budgets. Toward this goal, we present the case for building datacenters using processors and memories that were originally intended for mobile and embedded platforms. For web search, mobile processors are 5x more efficient than server processors. We quantify and mitigate the impact on query latency, relevance, and quality-of-service. Similarly, we identify datacenter applications that can benefit from mobile memories.
Mixing server and mobile hardware in a datacenter increases management complexity and we describe how datacenters might navigate this complexity with economic mechanisms. For settings where throughput is desired, we present a market in which users bid for heterogeneous hardware. For settings where fairness is desired, we present a game-theoretic mechanism that guarantees equitable hardware allocations. In both settings, we have devised strategy-proof mechanisms in which users cannot misrepresent their demands for hardware to manipulate system allocations.

Bio: Benjamin Lee is an assistant professor of Electrical and Computer Engineering at Duke University. His research focuses on scalable technologies, power-efficient architectures, and high-performance applications. He is also interested in the economics and public policy of computation. He has held visiting research positions at Microsoft Research, Intel Labs, and Lawrence Livermore National Lab.
Dr. Lee received his B.S. at the University of California at Berkeley, S.M. and Ph.D. at Harvard University, and post-doctorate at Stanford University. He received the NSF CAREER Award in 2012. And his research has been honored as a Top Pick by IEEE Micro Magazine (2010), twice as a Research Highlight by Communications of the ACM (2010, 2011), and by an NSF Computing Innovation Fellowship (2009-10).



"Application-Driven and Power-Aware Design of Multiprocessor Systems on Chip: A Biomedical Engineering Case Study"

Paolo Meloni (University of Cagliari)


Abstract: Bioengineering research is posing hard challenges to digital embedded system designers. Tight real-time constraints, miniaturization, and low power are critical issues exacerbated by applications requiring the implant of electronic devices in the patient’s body. Among them, neuro-controlled motor prostheses are on the cutting edge of the research in the field, requiring the real-time neural signal decoding to extract the patient’s movement intention in order to control the mechatronic device. Despite the literature in the field, how to implement a highly-portable and reliable integrated platform is still an open question. Within this research area, this lecture aims to present some novel solution for the application-driven power-aware design of MPSoCs.
Special emphasis will be put on runtime adaptation to different scenarios, characterized by different power budgets and performance requirement or by the detection of functional faults in the processing elements. As an application of such techniques, the lecture will present a field-programmable gate array-based prototype of an multi-processor system-on-chip embedded architecture that implements an online neural signal real-time decoding algorithm. Considering that the application workload is extremely data dependent and unpredictable, the architecture was dimensioned taking into account critical worst-case operating conditions to ensure robustness. To compensate the resulting over-provisioning of the system architecture the system embeds software-controllable power management. An evaluation of a prospective ASIC implementation of the system based on application specific instruction-set processors will be also presented.

Bio: Paolo Meloni is currently assistant professor at the Department of Electrical and Electronic Engineering (DIEE) in the University of Cagliari. From the same institution he received a Master degree in Electronic Engineering in October 2004, and a PhD in Electronic Engineering and Computer Science in October 2007, defending the thesis “Design and optimization techniques for VLSI network on chip architectures". He works at the EOLAB-Microelectronics Lab since November 2004. His research activity is mainly focused on the development of advanced digital systems, with special emphasis on the application-driven design of multi-core on-chip architectures. Within his research activity, he personally and directly cooperates on a daily bases with researches from first-class academic and industrial factors in the field of Electronic Engineering. He is author of several international research papers, reviewer for international scientific journals and conferences, and tutor of many bachelor and master students' thesis in Electronic Engineering. He is teaching the course of Embedded Systems at University of Cagliari and is currently part of the technical board and recently acted as work-package leader in the research projects ASAM ( and MADNESS (



"Crank It Up or Dial It Down: Coordinated Multiprocessor Frequency and Folding Control"

Augusto Vega (IBM Research)


Abstract: Dynamic power management features are now an integral part of processor chip and system design. Dynamic voltage and frequency scaling (DVFS), core folding and per-core power gating (PCPG) are power control actuators (or "knobs") that are available in modern multi-core systems. However, figuring out the actuation protocol for such knobs in order to achieve maximum efficiency has so far remained an open research problem. In the context of specific system utilization dynamics, the desirable order of applying these knobs is not easy to determine. For complexity-effective algorithm development, DVFS, core folding and PCPG control methods have evolved in a somewhat decoupled manner. However, as I will explain in this talk, independent actuation of these techniques can lead to conflicting decisions that jeopardize the system in terms of power-performance efficiency. Therefore, a more robust coordination protocol is necessary in orchestrating the power management functions. Heuristics for achieving such coordinated control are already becoming available in server systems. It remains an open research problem to optimally adjust power and performance management options at run-time for a wide range of time-varying workload applications, environmental conditions, and power constraints. In this talk, I will present a novel approach for a systematically architected, robust, multi-knob power management protocol, which was empirically analyzed on live server systems. We used a latest generation POWER7+ multi-core system to demonstrate the benefits of the proposed new coordinated power management algorithm (called PAMPA). Through measurement-based analysis, I will show that PAMPA achieves comparable power-performance efficiencies (relative to a baseline decoupled control system) while achieving conflict-free actuation and robust operation.

Bio: Augusto Vega is a Research Staff Member within the Reliability and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center. He has been involved in research and development work in support of IBM System p and Data Centric Systems. His primary focus area is power-aware computer architectures and associated system solutions. He has developed techniques to reduce chip power consumption in multicore/manycore chips for multi-threaded applications, exploiting core folding, frequency/voltage scaling and low-power ("sleep") modes. His research interests are in the areas of high performance, power/reliability-aware computer architectures, distributed and parallel computing, and performance analysis tools and techniques. In July 2013, he received a Ph.D. degree on Computer Architecture from Polytechnic University of Catalonia (UPC), Spain. Previously, he received a M.Sc. degree on Computer Architecture, Networks and Systems in 2009 from Polytechnic University of Catalonia (UPC), Spain.