HARSH 2014     


HARSH 2014 - Invited Speakers

"A View of System Software Design for next Generation High Efficient Systems"

Roberto Gioiosa (Pacific Northwest National Laboratory)

Roberto Gioiosa Abstract: In order to meet the expected level of performance under power and resiliency constraints the system software stack needs to be completely re-designed. Research studies stress the need of an introspective system that combines performance, power and resilience observations, in-situ analysis and dynamic generation of applications' performance and power models across all system stack layers with online feedback and adaptation mechanisms. However, the design and implementation of such system software is still an open research topics. Recent DOE ASCR projects (Argo and Hobbes) have started investigating possible solutions for exascale operating systems and adaptive runtimes. It seems reasonable to expect that exascale system will be required to dynamically and autonomously adapt to changing execution environments and/or applications' characteristics. Moreover, in order to achieve the desired level of power efficiency and correctness, a tight cooperation between all the layers in the system stack becomes essential.
In this talk, I will present a view of system software designs for high efficient systems, from exascale machines to high-end embedded systems. The main assumption is that, as systems become more and more complex and may run in constraint/hostile environment, the system software must be able to dynamically and autonomously adapt to changing execution environments. I will present our prototype self-aware/self-adaptive system and show how hardware/software co-design and a tight interaction among the system layers can increase the efficiency of high-efficient systems.

About the Speaker: Dr. Gioiosa is currently a research scientist at Pacific Northwest National Laboratory in the High Performance Computing group (Computational Science and Mathematics Division). Roberto received his Ph.D. on "High performance computing clusters" from the University of Rome "Tor Vergata" in 2006. Prior to coming to PNNL, he was graduate student at Los Alamos National Laboratory (LANL) from April 2004 to June 2005, working on High Performance Computing (fault tolerance and performance analysis) in the context of the PERCS project. Roberto worked at BSC as post-doc in 2006-2008 and 2009-2012; at BSC he worked on Operating Systems for High Performance Computing Clusters and optimization for future processor architectures and was involved in several projects with IBM, SUN, the European Union and the European Space Agency. From September 2008 to September 2009 he was post-doc at IBM TJ Watson Research center, in the BlueGene system software group, where he worked on the operating system for next generation of supercomputers BG/Q.
Roberto expertise covers system software (operating and runtime systems), computer architecture, performance analysis of high performance computing applications, power and resiliency analysis and runtime support for supercomputers.
He has served the high-performance and the computer architecture communities in various way (conference organization, technical program committee, workshop organizers). Roberto has published in the most important peer-reviewed conferences in the area of high-performance computing and computer architecture.

"Reconfigurable Computing in Memory for Improving Energy Efficiency and Reliability of Embedded Systems"

Prabhat Mishra (University of Florida)

Prabhat Mishra Abstract: Energy and reliability have emerged as two major considerations for embedded systems design. Energy saving directly translates into battery life improvement in mobile systems and mitigation of temperature-induced reliability concerns. Existing solutions for energy and reliability improvement in embedded systems are often not adequate for both compute- and data-intensive applications. Moreover, design techniques to achieve low power and reliable operation typically impose conflicting requirements. Increasing functional requirements of modern embedded systems to handle a wide variety of compute-intensive tasks coupled with ever-growing volume of data have created a critical need to explore novel low-cost design solutions to simultaneously achieve energy efficiency and reliability. In this talk, I will present a reconfigurable memory-based computing framework to address the energy and reliability issues. The basic idea is to use memory array as a malleable resource that can be used as either a custom computing or a data storage block. The reliability improvement is achieved through dynamic transfer of computations to memory when few functional units are defective or unreliable under process-induced or thermal variations. This also improves energy efficiency by bringing computation near the data, instead of bringing large volume of data to the processing units. This talk will cover three important aspects. First, I will provide an overview of memory-based computing (MBC). Next, I will describe promising approaches for designing efficient systems using MBC. Finally, I will present case studies to demonstrate that MBC can significantly improve reliability and energy efficiency of embedded systems.

About the Speaker: Prabhat Mishra is an Associate Professor in the Department of Computer and Information Science and Engineering (CISE) at the University of Florida (UF) where he leads the CISE Embedded Systems Lab. His research interests include design automation of embedded systems, energy-aware computing, reconfigurable architectures, security and reliability, hardware/software verification, and post-silicon debug.
He received his B.E. from Jadavpur University, Kolkata in 1994, M.Tech. from the Indian Institute of Technology, Kharagpur in 1996, and Ph.D. from the University of California, Irvine in 2004 -- all in Computer Science and Engineering. Prior to joining University of Florida, he spent several years in various companies including Intel, Motorola, Synopsys and Texas Instruments. He has published four books, ten book chapters and more than 100 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, two best paper awards (VLSI Design 2011 and CODES+ISSS 2003), several best paper award nominations (including DAC'09 and DATE'12), and 2004 EDAA Outstanding Dissertation Award from the European Design Automation Association. He has also received the 2007 International Educator of the Year Award from the UF College of Engineering for his significant international research and teaching contributions.

"Autonomic Refurbishment of Reconfigurable Datapaths for High-Availability Mission-Critical Architectures"

Ronald F. DeMara (University of Central Florida)

Prabhat Mishra Abstract: In this talk, autonomous techniques for high-availability embedded architectures with nanometer scaling are presented. The focus is on maintaining both quality and throughput requirements despite vulnerabilities of the underlying computational devices. Online resiliency techniques using partial reconfiguration of SRAM-based FPGA fabrics offer a promising approach to meet these objectives. They enable the benefits of priority-aware resiliency over conventional redundancy in terms of fault recovery, energy consumption, and area requirements. It is advocated that reconfigurable fabrics can host a hierarchy of resource monitoring, escalation, and refurbishment techniques. These include dynamic reconfiguration of Amorphous Spares which provide a desirable alternative to design-time allocation of redundancy.
It will be shown how fault detection can be accomplished using only a uniplex hardware arrangement which neither requires test vectors nor suspends the computational throughput. Thus, mission-critical objectives of high availability are achieved. These approaches are validated for a Discrete Cosine Transform (DCT) block, image processing workloads, and MCNC benchmark circuits. For image processing applications, the peak signal-to-noise ratio is demonstrated as a health metric to achieve the desired objectives during the isolation and recovery phases. The diagnosability, reconfiguration latency, and resource overheads are analyzed to illustrate the benefits of these techniques and their costs.

About the Speaker: Ronald F. DeMara received the Ph.D. degree in Computer Engineering from the University of Southern California in 1992. Since 1993, he has been a full-time faculty member at the University of Central Florida. He is a Professor in the Department of Electrical Engineering and Computer Science and also serves as Computer Engineering Coordinator. His research interests are in Adaptive Computer Architectures, Evolvable Hardware, and Distributed Architectures for Intelligent Systems. He has published approximately 140 articles in journals and conferences on these topics, and holds one patent. His research has been sponsored by the National Science Foundation; NASA; the U.S. Army, Navy, Air Force, DARPA, and others.
He is a Senior Member of IEEE, a Member of ACM and ASEE, and Associate Editor of IEEE Transactions on Computers. He has also served as Associate Editor of IEEE Transactions on VLSI Systems, the Journal of Circuits, Systems, and Computers, and the journal Microprocessors and Microsystems, and as Associate Guest Editor of ACM Transactions on Embedded Computing Systems. He served on conference Program Committees including the IEEE Congress on Evolutionary Computation (ICES), International Conference on Field Programmable Logic and Applications (FPL), NASA/DoD Conference on Evolvable Hardware (EH), International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), and on the Executive Committee of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), and was keynote speaker at the International Conference on Reconfigurable Computing and FPGAs (ReConFig). In 2008, he received the Joseph M. Biedenbach Outstanding Engineering Educator Award from IEEE in Region 3.

"Multicore Systems for Harsh Environments"

Mladen Berekovic (TU Braunschweig)

Mladen Berekovic Abstract: With increasing capabilities and miniaturization, multicore systems are being deployed in an ever increasing range of systems and applications: From avionics and cars to health and fitness sensors. In fact, the development of multicore Systems is even driving the development of new applications such as fitness sensors. This trend poses new challenges on the design of such systems in terms of complexity, costs and design methodology. The integration of multicore systems in harsh environments however has several specific implications. The integration of complex control functionalities on a multi-core implies the integration of functionalities with different criticality on a single processing device. Traditional general-purpose computing architectures do not satisfy these requirements. Also power efficiency becomes a concern, especially when tasks with mixed criticality are running concurrently and deadlines have to be kept within a specific power budget (e.g. in mobile systems). Programming models and memory systems have to support the high levels of on-chip parallelism while special measures for fault tolerance ned to be employed. I will present two design examples: RC64: ESAs next generation high-perforamnce DSP for space and IDA-NOC that was developed within the European RECOMP project. Finally, design methodologies have to be adapted to cope with the increasing complexity in combination with strict safety requirements. Recent advances in Electronic System Level (ESL) Design provide new opportunities for the prototyping and exploration of complex multicore system designs, as will be shown with ESAs SoCRocket framework.

About the Speaker: Mladen Berekovic received his MS and PhD degrees from University of Hannover, Germany, where he worked on parallel DSPs for Video processing and SAR After that he worked at IBM in processor development before he went to IMEC where he was leading teams on parallel DSP architectures for mobile applications. Since 2007 he is with TU Braunschweig, where he is heading the computer engineering group. His research interests include parallel & fault tolerant processor architectures for safety-critical applications.

"Thread Placement Strategies to Augment Power/Thermal Efficiency"

Augusto Vega (IBM T. J. Watson Research Center)

Augusto Vega Abstract: Systems designed to operate under harsh operating conditions (or in lower cost data center installations) are often faced with the prospect of higher-than-desirable chip temperatures. This can lead to higher leakage power and hence higher system power. Higher temperatures are also associated with higher failure rates; and this might make it hard to meet system resilience specifications. One way to combat this problem is to invest in aggressive chip-embedded cooling solutions when it comes to processor chip design. In addition to improved cooling, intelligent thread placement strategies can reduce power (and temperature) without compromising system performance. IBM is exploring these approaches including both technology options (chip embedded cooling solutions) and architectural options (intelligent thread placement strategies). This talks provides an overview of both approaches.

About the Speaker: Augusto Vega is a Research Staff Member within the Reliability and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center. He has been involved in research and development work in support of IBM System p and Data Centric Systems. His primary focus area is power-aware computer architectures and associated system solutions. He has developed techniques to reduce chip power consumption in multicore/manycore chips for multi-threaded applications, exploiting core folding, frequency/voltage scaling and low-power ("sleep") modes. His research interests are in the areas of high performance, power/reliability-aware computer architectures, distributed and parallel computing, and performance analysis tools and techniques.
He received a Ph.D. degree on "Computer Architecture" and a M.Sc. degree on "Computer Architecture, Networks and Systems" from Polytechnic University of Catalonia (UPC), Spain.