FastPath 2015 - Speakers
"CoRAM: An FPGA Architecture for Computing"
Abstract: Despite their promise in both processing performance and efficiency, today's FPGAs remain poorly matched to serve as computing devices. This is especially noticeable in their lack of an appropriate native memory architecture. The CoRAM (Connected RAM) project has been rethinking the FPGA architecture from scratch for a new generation of first-class reconfigurable computing devices. This talk will present the CoRAM FPGA architecture and its high-level memory abstraction that serves as a portable, high-performance bridge between the distributed in-fabric computation kernels and the off-chip DRAM. The talk will discuss a current effort to support the CoRAM abstraction on the hardware of near-term commercially available FPGAs. Please see the CoRAM project page (http://www.ece.cmu.edu/~coram) for more information including online demos and tutorials.
Bio: James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University. He received his Ph.D. in EECS from Massachusetts Institute of Technology in 2000 (S.M., 1994). He received his B.S. in EECS from UC Berkeley in 1992. He is interested in many aspects of computer architecture and digital hardware design, including the specific areas of FPGA architecture for computing; digital signal processing hardware; and high-level hardware design and synthesis. He co-directs the Computer Architecture Lab at Carnegie Mellon (CALCM) and is affiliated with the Center for Silicon System Implementation (CSSI). He is a Fellow of IEEE. For more information, please visit http://www.ece.cmu.edu/~jhoe.
"Designing Multicore Processors for Networking, Servers, and Beyond"
Abstract: The design of CPUs has always required a balance of performance and efficiency in power, area, and complexity. The emergence of multicore SoCs armed with network accelerators and virtualization and demands of the cloud market have shifted this balance from solely single-thread performance to a combination of single-thread performance and efficient parallel processing. This shift requires a new style of core with short and deterministic pipelines, caches and memory systems optimized for low latency and high bandwidth, and an architecture that scales to 48-plus cores on a chip. This talk will describe how Cavium’s processor design matches the evolving demands from cloud and networking markets.
Bio: Dr. Shubu Mukherjee is one of Cavium Inc.s Distinguished Engineers and lead core architect for OCTEON-III and ThunderX family of processors. Shubu is the winner of the ACM SIGARCH Maurice-Wilkes award, a Fellow of ACM, a Fellow of IEEE, and the author of the book Architecture Design for Soft Errors. Shubu holds 33 patents and has written over 50 technical papers in top architecture conference and journals. Before joining Cavium in May 2010, Shubu worked at Intel for 9 years and Compaq for 3 years. He received his MS and Phd from the University of Wisconsin-Madison and his B.Tech., from the Indian Institute of Technology, Kanpur.
"Achieving QoS in Server Platforms: From Concept to Reality"
Abstract: In this talk, I will describe the quality-of-service (QoS) challenges when running multiple workloads simultaneously on servers and datacenters. I will outline the research and development efforts for monitoring and enforcing allocation of shared resources such as shared cache space and memory bandwidth. In particular, I will also describe our recent server platform where cache monitoring and allocation techniques (CMT, CAT) were integrated and how these techniques enable better quality-of-service solutions for datacenters. I will also touch upon potential future work in this area of QoS and beyond, specifically focusing in on domain-specific workload optimization opportunities in cloud platforms.
Bio: Ravi Iyer is a Senior Principal Engineer and Director of the SoC Platform Architecture group in Intel Labs. He conducts research on future SoC and CMP architectures, ultra-small cores, accelerators, innovative cache/memory hierarchies, interconnect fabrics, workload characterization, emerging devices, and power/performance evaluation. Ravi is also the Managing Sponsor for two research centers: the Intel Science and Technology Center for Embedded Computing (ISTC-EC) at Carnegie Mellon University and the Intel Collaborative Research Institute for Computational Intelligence (ICRI-CI) in Israel. Ravi frequently participates in journals, conferences and workshops. He has published 140+ technical papers and has 40+ patent applications pending. Ravi is currently an associate editor for ACM TACO.
He recently served as the General Co-Chair for ISCA 2011 and the Program Co-Chair for ANCS 2010. Ravi has served on program committees for many conferences (MICRO, HPCA, PACT, ISPASS and others) and has co-chaired several workshops (SHAW, CAECW, BEACON). He collaborates with several academic groups on architecture research for CMP and SoC platforms. He has also mentored and advised Ph.D students and has sat on several dissertation committees. Ravi received his Ph.D. in Computer Science from Texas A&M University. Ravi is a senior member of the IEEE.
"Software and System Co-optimization in the era of Heterogeneous Computing"
Abstract: Escalating costs of semiconductor technology and its lagging performance relative to historic trends is motivating acceleration and specialization as more impactful means to increase system value. Targeted specialization is being increasingly pursued as an important way to achieve dramatic improvements in workload acceleration. This requires a broad understanding of workloads, system structures, and algorithms to determine what to accelerate / specialize, and how, i.e., via SW?; via HW?; or via SW+HW? which presents many choices, necessitating co-optimization of SW and HW. In this talk, we will focus on an application driven approach to software and system co-optimization, based on inventing new software algorithms, that have strong affinity to hardware acceleration. A High Level design methodology that is needed to enable targeted specialization in hardware will also be described.
Bio: Ruchir Puri is an IBM Fellow at IBM Thomas J. Watson Research Center, Yorktown Hts, NY where he leads high performance design and methodology solutions for all of IBM’s enterprise server and system chip designs. Most recently, he led the design methodology innovations for IBM’s latest Power7 and zEnterprise microprocessors and is currently leading design methodology research efforts on future processors. Dr. Puri has received numerous accolades including the highest technical position at IBM, the IBM Fellow, which was awarded for his transformational role in microprocessor design methodology. In addition, Dr. Puri has received “Best of IBM” awards in both 2011 and 2012 and IBM Corporate Award from IBM’s CEO, and several IBM Outstanding Technical Achievement awards. Dr. Ruchir Puri is a Fellow of the IEEE, a member of IBM Academy of Technology and IBM Master Inventor, an ACM Distinguished Speaker and IEEE Distinguished Lecturer. He is also a recipient of SRC outstanding mentor award and have been an adjunct professor at Dept. of Electrical Engineering, Columbia University, NY and was also honored with John Von-Neumann Chair at Institute of Discrete Mathematics at Bonn University, Germany. Ruchir also received 2014 Asian American Engineer of the Year Award. He has delivered numerous keynotes and invited talks at major VLSI Design and Automation conferences, National Science Foundation and US Department of Defense Research panels and have been an editor of IEEE Transactions on Circuits and Systems. Dr. Puri is an inventor of over 50 U.S. patents (both issued and pending) and have authored over 100 publications on the design and synthesis of low-power and high-performance circuits. Ruchir is very passionate about technology among school children and has been evangelizing fun with electronics and FIRST LEGO LEAGUE Robotics in community schools.