Avi Ziv
contact information
Research Staff Member, Verification and Quality TechnologiesHaifa Research Lab, Haifa, Israel +972
4
829
6454



links
Professional Associations
Professional Associations: ACM SIGDA | IEEE Computer Society | IEEE, Senior Member2012
Checking architectural outputs instruction-by-instruction on acceleration platforms
Proceedings of the 49th ..., 2012 - dl.acm.org
Proceedings of the 49th ..., 2012 - dl.acm.org
Optimizing test-generation to the execution platform
A. Nahir, A. Ziv, S. Panda
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, pp. 304--309
A. Nahir, A. Ziv, S. Panda
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, pp. 304--309
Generating instruction streams using abstract CSP
Y. Katz, M. Rimon, A. Ziv
Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2012, pp. 15--20
Y. Katz, M. Rimon, A. Ziv
Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2012, pp. 15--20
2011
Learning microarchitectural behaviors to improve stimuli generation quality
Y. Katz, M. Rimon, A. Ziv, G. Shaked
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 848--853
Y. Katz, M. Rimon, A. Ziv, G. Shaked
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 848--853
Concurrent Generation of Concurrent Programs for Post-Silicon Validation
Allon Adir, Amir Nahir, Avi Ziv
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 31(8), 1297--1302, IEEE, 2011
Allon Adir, Amir Nahir, Avi Ziv
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 31(8), 1297--1302, IEEE, 2011
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
A. Adir, A. Nahir, G. Shurek, A. Ziv, C. Meissner, J. Schumann
Proceedings of the 48th Design Automation Conference, pp. 569--574, 2011
A. Adir, A. Nahir, G. Shurek, A. Ziv, C. Meissner, J. Schumann
Proceedings of the 48th Design Automation Conference, pp. 569--574, 2011
Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems
K.D. Schubert, W. Roesner, J.M. Ludden, J. Jackson, J. Buchert, V. Paruthi, M. Behm, A. Ziv, J. Schumann, C. Meissner, others
IBM Journal of Research and Development 55(3), 10--1, IBM, 2011
K.D. Schubert, W. Roesner, J.M. Ludden, J. Jackson, J. Buchert, V. Paruthi, M. Behm, A. Ziv, J. Schumann, C. Meissner, others
IBM Journal of Research and Development 55(3), 10--1, IBM, 2011
Threadmill: A post-silicon exerciser for multi-threaded processors
A. Adir, M. Golubev, S. Landa, A. Nahir, G. Shurek, V. Sokhin, A. Ziv
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 860--865
A. Adir, M. Golubev, S. Landa, A. Nahir, G. Shurek, V. Sokhin, A. Ziv
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pp. 860--865
A unified methodology for pre-silicon verification and post-silicon validation
A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann
Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2011, pp. 1--6
A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann
Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2011, pp. 1--6
Automatic Boosting of Cross-Product Coverage Using Bayesian Networks
Dorit Baras, Shai Fine, Laurent Fournier, Dan Geiger, Avi Ziv
International Journal on Software Tools for Technology Transfer (STTT) 13(3), 247--261, Springer, 2011
Dorit Baras, Shai Fine, Laurent Fournier, Dan Geiger, Avi Ziv
International Journal on Software Tools for Technology Transfer (STTT) 13(3), 247--261, Springer, 2011
2010
Bridging pre-silicon verification and post-silicon validation
A Nahir, A Ziv, M Abramovici, A Camilleri, R Galivanche, B Bentley, H Foster, A Hu, V Bertacco, S Kapoor
Design Automation Conference (DAC), 2010 47th ACM/IEEE, pp. 94--95
A Nahir, A Ziv, M Abramovici, A Camilleri, R Galivanche, B Bentley, H Foster, A Hu, V Bertacco, S Kapoor
Design Automation Conference (DAC), 2010 47th ACM/IEEE, pp. 94--95
Reaching coverage closure in post-silicon validation
A Adir, A Nahir, A Ziv, C Meissner, J Schumann
Hardware and Software: Verification and Testing, 60--75, Springer, 2010
A Adir, A Nahir, A Ziv, C Meissner, J Schumann
Hardware and Software: Verification and Testing, 60--75, Springer, 2010
2009
Using Bayesian networks and virtual coverage to hit hard-to-reach events
S Fine, L Fournier, A Ziv
International Journal on Software Tools for Technology Transfer (STTT) 11(4), 1--15, Springer, 2009
S Fine, L Fournier, A Ziv
International Journal on Software Tools for Technology Transfer (STTT) 11(4), 1--15, Springer, 2009
2008
Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution
A. Hunter, A. Piziali, A. Ziv, K. Larson, S. Hemmady
Microprocessor Test and Verification, 2008. MTV'08. Ninth International Workshop on, pp. 7--13
A. Hunter, A. Piziali, A. Ziv, K. Larson, S. Hemmady
Microprocessor Test and Verification, 2008. MTV'08. Ninth International Workshop on, pp. 7--13
A probabilistic alternative to regression suites
S. Copty, S. Fine, S. Ur, E. Yom-Tov, A. Ziv
Theoretical Computer Science 404(3), 219--234, Elsevier, 2008
S. Copty, S. Fine, S. Ur, E. Yom-Tov, A. Ziv
Theoretical Computer Science 404(3), 219--234, Elsevier, 2008
Using virtual coverage to hit hard-to-reach events
Laurent Fournier, Avi Ziv
Hardware and Software: Verification and Testing, pp. 104--119, Springer, 2008
Laurent Fournier, Avi Ziv
Hardware and Software: Verification and Testing, pp. 104--119, Springer, 2008
2007
Verification Coverage: When is Enough, Enough?
F. Bacchini, A.J. Hu, T. Fitzpatrick, R. Ranjan, D. Lacey, M. Tan, A. Piziali, A. Ziv
Design Automation Conference, 2007. DAC'07. 44th ACM/IEEE, pp. 744--745
F. Bacchini, A.J. Hu, T. Fitzpatrick, R. Ranjan, D. Lacey, M. Tan, A. Piziali, A. Ziv
Design Automation Conference, 2007. DAC'07. 44th ACM/IEEE, pp. 744--745
2006
Using Linear Programming Techniques for Scheduling-Based Random Test-Case Generation
Amir Nahir, Yossi Shiloach, Avi Ziv
Haifa Verification Conference, pp. 16-33, Springer, 2006
Amir Nahir, Yossi Shiloach, Avi Ziv
Haifa Verification Conference, pp. 16-33, Springer, 2006
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation
Shai Fine, Ari Freund, Itai Jaeger, Yishay Mansour, Yehuda Naveh, Avi Ziv
IEEE Transactions on Computers 55(11), 1344-1355, Institute of Electrical and Electronics Engineers, 2006
Shai Fine, Ari Freund, Itai Jaeger, Yishay Mansour, Yehuda Naveh, Avi Ziv
IEEE Transactions on Computers 55(11), 1344-1355, Institute of Electrical and Electronics Engineers, 2006
Scheduling-based test-case generation for verification of multimedia SoCs
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen
DAC, pp. 348-351, 2006
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen
DAC, pp. 348-351, 2006
Advanced analysis techniques for cross-product coverage
H Azatchi, L Fournier, E Marcus, S Ur, A Ziv, K Zohar
IEEE Transactions on Computers 55(11), 1367--1379, IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS, 2006
H Azatchi, L Fournier, E Marcus, S Ur, A Ziv, K Zohar
IEEE Transactions on Computers 55(11), 1367--1379, IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS, 2006
2005
Harnessing machine learning to improve the success rate of stimuli generation
Shai Fine, Ari Freund, Itai Jaeger, Yehuda Naveh, Avi Ziv, Yishay Mansour
IEEE International High-Level Design Validation and Test Workshop, pp. 112--118, IEEE, 2005
US Patent App. 20,070/011,631
Shai Fine, Ari Freund, Itai Jaeger, Yehuda Naveh, Avi Ziv, Yishay Mansour
IEEE International High-Level Design Validation and Test Workshop, pp. 112--118, IEEE, 2005
US Patent App. 20,070/011,631
2004
Stimuli generation with late binding of values
A Ziv
Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 10558
A Ziv
Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 10558
Probabilistic regression suites for functional verification
Shai Fine, Shmuel Ur, Avi Ziv
Proceedings of the 41st annual Design Automation Conference, pp. 49-54, Google Patents, 2004
US Patent App. 11/145,866
Shai Fine, Shmuel Ur, Avi Ziv
Proceedings of the 41st annual Design Automation Conference, pp. 49-54, Google Patents, 2004
US Patent App. 11/145,866
Object-oriented high-level modeling of an InfiniBand to PCI-X bridge
O. Lachish, A. Ziv
Proc, pp. 243--253, Springer, 2004
O. Lachish, A. Ziv
Proc, pp. 243--253, Springer, 2004
Enhancing the efficiency of Bayesian network based coverage directed test generation
M Braun, S Fine, A Ziv, STZ Softwaretechnik, G Esslingen
Ninth IEEE International High-Level Design Validation and Test Workshop, 2004, pp. 75--80
M Braun, S Fine, A Ziv, STZ Softwaretechnik, G Esslingen
Ninth IEEE International High-Level Design Validation and Test Workshop, 2004, pp. 75--80
Defining coverage views to improve functional coverage analysis
S. Asaf, E. Marcus, A. Ziv
Proceedings of the 41st annual Design Automation Conference, pp. 41--44, 2004
S. Asaf, E. Marcus, A. Ziv
Proceedings of the 41st annual Design Automation Conference, pp. 41--44, 2004
Genesys-pro: Innovations in test program generation for functional processor verification
Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv
Design \& Test of Computers, IEEE 21(2), 84--93, IEEE, 2004
Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv
Design \& Test of Computers, IEEE 21(2), 84--93, IEEE, 2004
2003
What's the next'big thing'in simulation-based verification?
M. Levinger, A. Ziv, B. Bailey, J. Abraham, B. Joyner, Y. Kas
Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop, pp. 175, 2003
M. Levinger, A. Ziv, B. Bailey, J. Abraham, B. Joyner, Y. Kas
Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop, pp. 175, 2003
Functional verification environment for objectoriented hardware designs
A. Ziv
Forum on Design Languages (FDL), 2003
A. Ziv
Forum on Design Languages (FDL), 2003
What's the next'big thing'in simulation-based verification?
M Levinger, A Ziv, B Bailey, J Abraham, B Joyner, Y Kas
hldvt, pp. 175--175, 2003
M Levinger, A Ziv, B Bailey, J Abraham, B Joyner, Y Kas
hldvt, pp. 175--175, 2003
Functional Verification Environment for Object-oriented Hardware Designs
A Ziv
Forum on Design Languages {(FDL)}, 2003
A Ziv
Forum on Design Languages {(FDL)}, 2003
Enhancing the control and efficiency of the covering process [logic verification]
S. Fine, A. Ziv
High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International, pp. 96--101
S. Fine, A. Ziv
High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International, pp. 96--101
Enhancing the control and efficiency of the covering process
S Fine, A Ziv
IEEE International High-Level Validation and Test Workshop (HLDVT 2003), pp. 96--101
S Fine, A Ziv
IEEE International High-Level Validation and Test Workshop (HLDVT 2003), pp. 96--101
Piparazzi: A Test Program Generator for Micro-architecture Flow Verification
A.A.E.B.O. Peled, A. Ziv
High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International, pp. 23--28
A.A.E.B.O. Peled, A. Ziv
High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International, pp. 23--28
Coverage directed test generation for functional verification using bayesian networks
Shai Fine, Avi Ziv
Proceedings of the 40th Design Automation Conference (DAC'03), pp. 286-291, 2003
Shai Fine, Avi Ziv
Proceedings of the 40th Design Automation Conference (DAC'03), pp. 286-291, 2003
Cross-product functional coverage measurement with temporal properties-based assertions
A. Ziv
Proceedings of the conference on Design, Automation and Test in Europe-Volume 1, pp. 10834, 2003
A. Ziv
Proceedings of the conference on Design, Automation and Test in Europe-Volume 1, pp. 10834, 2003
2002
Using Temporal Checkers for Functional Coverage
A. Ziv
Proc. Intn’l Workshop on Microprocessor Test and Verification, Citeseer, 2002
A. Ziv
Proc. Intn’l Workshop on Microprocessor Test and Verification, Citeseer, 2002
Cross-Fertilization between Hardware Verification and Software Testing
S Ur, A Ziv
6th IASTED International Conference on Software Engineering and Applications (SEA2002)
S Ur, A Ziv
6th IASTED International Conference on Software Engineering and Applications (SEA2002)
Hole analysis for functional coverage data
O. Lachish, E. Marcus, S. Ur, A. Ziv
Design Automation Conference, 2002. Proceedings. 39th, pp. 807--812
O. Lachish, E. Marcus, S. Ur, A. Ziv
Design Automation Conference, 2002. Proceedings. 39th, pp. 807--812
Using a constraint satisfaction formulation and solution techniques for random test program generation
E. Bin, R. Emek, G. Shurek, A. Ziv
IBM Systems Journal 41(3), 386--402, IBM, 2002
E. Bin, R. Emek, G. Shurek, A. Ziv
IBM Systems Journal 41(3), 386--402, IBM, 2002
2001
Cost evaluation of coverage directed test generation for the IBM mainframe
G. Nativ, S. Mittennaier, S. Ur, A. Ziv
Test Conference, 2001. Proceedings. International, pp. 793--802
G. Nativ, S. Mittennaier, S. Ur, A. Ziv
Test Conference, 2001. Proceedings. International, pp. 793--802
Cost Evaluation of Coverage-Directed Test Generation for the IBM Mainframe
G Nativ, S Mittermaier, S Ur, A Ziv
International Test Conference, pp. 793--802, 2001
G Nativ, S Mittermaier, S Ur, A Ziv
International Test Conference, pp. 793--802, 2001
1999
Short vs long size does make a difference
A Hartman, S Ur, A Ziv
Proceedings of the High-Level Design Validation and Test Workshop, pp. 23--28, 1999
A Hartman, S Ur, A Ziv
Proceedings of the High-Level Design Validation and Test Workshop, pp. 23--28, 1999
1998
Design reliability-estimation through statistical analysis of bug discovery data
Y. Malka, A. Ziv
Design Automation Conference, 1998. Proceedings, pp. 644--649
Y. Malka, A. Ziv
Design Automation Conference, 1998. Proceedings, pp. 644--649
User defined coverage—a tool supported methodology for design verification
R. Grinwald, E. Harel, M. Orgad, S. Ur, A. Ziv
Proceedings of the 35th annual Design Automation Conference, pp. 158--163, 1998
R. Grinwald, E. Harel, M. Orgad, S. Ur, A. Ziv
Proceedings of the 35th annual Design Automation Conference, pp. 158--163, 1998
Analysis of checkpointing schemes with task duplication
A. Ziv, J. Bruck
Computers, IEEE Transactions on 47(2), 222--227, IEEE, 1998
A. Ziv, J. Bruck
Computers, IEEE Transactions on 47(2), 222--227, IEEE, 1998
Design reliability—estimation through statistical analysis of bug discovery data
Y Malka, A Ziv
Proceedings of the 35th annual Design Automation Conference, pp. 644--649, 1998
Y Malka, A Ziv
Proceedings of the 35th annual Design Automation Conference, pp. 644--649, 1998
Off-the-shelf vs. custom made coverage models, which is the one for you
S Ur, A Ziv
proceedings of STAR98: the 7th international conference on software testing analysis and review, 1998
S Ur, A Ziv
proceedings of STAR98: the 7th international conference on software testing analysis and review, 1998
User defined coverage-a tool supported methodology for design verification
M Orgad, A Ziv, S Ur, E Harel, R Grinwald
dac, pp. 158--163, 1998
M Orgad, A Ziv, S Ur, E Harel, R Grinwald
dac, pp. 158--163, 1998
1997
Performance optimization of checkpointing schemes with task duplication
A. Ziv, J. Bruck
Computers, IEEE Transactions on 46(12), 1381--1386, IEEE, 1997
A. Ziv, J. Bruck
Computers, IEEE Transactions on 46(12), 1381--1386, IEEE, 1997
1996
Checkpointing in Parallel and Distributed Systems
A. Ziv and J. Bruck
Parallel and distributed computing handbook, pp. 274-302, McGraw-Hill Professional, 1996
A. Ziv and J. Bruck
Parallel and distributed computing handbook, pp. 274-302, McGraw-Hill Professional, 1996
An on-line algorithm for checkpoint placement
A Ziv, J Bruck
The Seventh International Symposium on Software Reliability Engineering, pp. 274--283} MONTH = {November, IEEE, 1996
A Ziv, J Bruck
The Seventh International Symposium on Software Reliability Engineering, pp. 274--283} MONTH = {November, IEEE, 1996
1995
Analysis and performance optimization of checkpointing schemes with task duplication
A. Ziv
Ph.D. Thesis, Stanford University Stanford, CA, USA, 1995
A. Ziv
Ph.D. Thesis, Stanford University Stanford, CA, USA, 1995
1994
Placement and routing for a field programmable multi-chip module
S Lan, A Ziv, A El Gamal
Design Automation, 1994, pp. 295--300
S Lan, A Ziv, A El Gamal
Design Automation, 1994, pp. 295--300
Efficient checkpointing over local area networks
A. Ziv, J. Bruck
Fault-Tolerant Parallel and Distributed Systems, 1994., Proceedings of IEEE Workshop on, pp. 30--35
A. Ziv, J. Bruck
Fault-Tolerant Parallel and Distributed Systems, 1994., Proceedings of IEEE Workshop on, pp. 30--35
Analysis of checkpointing schemes for multiprocessor systems
A Ziv, J Bruck
Proceeding of the 13th Symposium on Reliable Distributed Systems, pp. 52--61, 1994
A Ziv, J Bruck
Proceeding of the 13th Symposium on Reliable Distributed Systems, pp. 52--61, 1994