Rahul M Rao  Rahul M Rao photo         

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Senior Technical Staff Memer, Enterprise Systems Development
Bangalore, India
  +91dash80dash406dash61261

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Professional Associations

Professional Associations:  ACM  |  IEEE Member


2018

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4
Christopher Gonzalez, Michael Floyd, Eric Fluhr, Phillip Restle, Daniel Dreps, Michael Sperling, Rahul Rao, David Hogenmiller, Christos Vezyrtis, Pierce Chuang, others
IEEE Journal of Solid-State Circuits 53(1), 91--101, IEEE, 2018

Impact of Device Aging on Early Mode Failures in Pulsed Latches
Ankur Shukla, Rahul M Rao, James D Warnock
2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 256--260

IBM POWER9 circuit design and energy optimization for 14-nm technology
EJ Fluhr, RM Rao, H Smith, A Buyuktosunoglu, R Bertran
IBM Journal of Research and Development, IBM, 2018


2017

Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics
Sumantra Sarkar, Ayan Biswas, Anindya Sundar Dhar, Rahul M Rao
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25(11), 3057--3066, IEEE, 2017

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4
Christopher Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul Rao, Jose Paredes, Michael Floyd, Michael Sperling, Ryan Kruse, Vinod Ramadurai, others
Solid-State Circuits Conference (ISSCC), 2017 IEEE International, pp. 50--51


2016

FVCAG: A framework for formal verification driven power modeling and verification
Arun Joseph, Spandana Rachamalla, Rahul M Rao, Anand Haridass, Pradeep K Nalla
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, pp. 260--265


2015

IBM POWER8 circuit design and energy optimization
V Zyuban, Joshua Friedrich, Daniel M Dreps, J\"urgen Pille, Donald W Plass, Phillip J Restle, Zeynep Toprak Deniz, Matthew M Ziegler, S Chu, S Islam, others
IBM Journal of Research and Development 59(1), 9--1, IBM, 2015

Virtual logic netlist: Enabling efficient RTL analysis
Spandana Rachamalla, Arun Joseph, Rahul Rao, Diwesh Pandey
Quality Electronic Design (ISQED), 2015 16th International Symposium on, pp. 571--576


2014

Introduction to special issue on reliability and device degradation in emerging technologies
Rahul Rao, Fadi Gebara
ACM Journal on Emerging Technologies in Computing Systems (JETC) 10(1), 1, ACM, 2014

ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume 10 Issue 1
Rahul Rao, Fadi Gebara, Alberto Avritzer, Tadashi Dohi
ACM, 2014


2013

Slew-rate monitoring circuit for on-chip process variation detection
Amlan Ghosh, Rahul M Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B Brown
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21(9), 1683--1692, IEEE, 2013

IBM POWER7+ design for higher frequency at fixed power
V Zyuban, Scott A Taylor, Birger Christensen, AR Hall, Christopher J Gonzalez, Joshua Friedrich, Frances Clougherty, Jon Tetzloff, R Rao
IBM Journal of Research and Development 57(6), 1--1, IBM, 2013

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator
Yuma Higuchi, Ken-ichi Shinkai, Masanori Hashimoto, Rahul Rao, Sani Nassif
Test Symposium (ETS), 2013 18th IEEE European, pp. 1--6


2012

Impact of die-to-die thermal coupling on the electrical characteristics of 3D stacked SRAM cache
Subho Chatterjee, Minki Cho, Rahul Rao, Saibal Mukhopadhyay
Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2012 28th Annual IEEE, pp. 14--19

Usage-based degradation of SRAM arrays due to bias temperature instability
Aditya Bansal, Jae-Joon Kim, Rahul Rao
Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. 2F--6


2011

SRAM write-ability improvement with transient negative bit-line voltage
Saibal Mukhopadhyay, Rahul M Rao, Jae-Joon Kim, Ching-Te Chuang
IEEE transactions on very large scale integration (VLSI) systems 19(1), 24--32, IEEE, 2011

Reliability monitoring ring oscillator structures for isolated/combined NBTI and PBTI measurement in high-k metal gate technologies
Jae-Joon Kim, Barry P Linder, Rahul M Rao, Tae-Hyoung Kim, Pong-Fei Lu, Keith A Jenkins, Chris H Kim, Aditya Bansal, Saibal Mukhopadhyay, Ching-Te Chuang
Reliability Physics Symposium (IRPS), 2011 IEEE International, pp. 2B--4

PBTI/NBTI monitoring ring oscillator circuits with on-chip Vt characterization and high frequency AC stress capability
Jae-Joon Kim, Rahul M Rao, Jeremy Schaub, Amlan Ghosh, Aditya Bansal, Kai Zhao, Barry P Linder, James Stathis
VLSI Circuits (VLSIC), 2011 Symposium on, pp. 224--225

Variations: sources and characterization
Aditya Bansal, Rahul M Rao
Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 3--39, Springer, Boston, MA, 2011

Power optimization methodology for the IBM POWER7 microprocessor
V Zyuban, J Friedrich, CJ Gonzalez, R Rao, MD Brown, MM Ziegler, H Jacobson, S Islam, S Chu, P Kartschoke, others
IBM Journal of Research and Development 55(3), 7--1, IBM, 2011

Separating NBTI and PBTI effects on the degradation of ring oscillator frequency
Barry P Linder, Jae-Joon Kim, Rahul Rao, Keith Jenkins, Aditya Bansal
Integrated Reliability Workshop Final Report (IRW), 2011 IEEE International, pp. 1--6

Bias Temperature Instability model for digital circuits-predicting instantaneous FET response
Aditya Bansal, Kai Zhao, Jae-Joon Kim, Rahul Rao
Reliability Physics Symposium (IRPS), 2011 IEEE International, pp. CR--2

A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS
DP Ioannou, K Zhao, A Bansal, B Linder, R Bolam, E Cartier, J-J Kim, R Rao, G La Rosa, G Massey, others
Reliability Physics Symposium (IRPS), 2011 IEEE International, pp. CR--1


2010

Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
Harmander Singh, Rahul Rao, Kanak Agarwal, Dennis Sylvester, Richard Brown
IEEE transactions on very large scale integration (VLSI) systems 18(1), 166--170, IEEE, 2010

Guest editors' introduction: Managing uncertainty through postfabrication calibration and repair
Swarup Bhunia, Rahul Rao
IEEE Design \& Test of Computers 27(6), 4--5, IEEE, 2010

4 Guest Editors’ Introduction: Managing Uncertainty through Postfabrication Calibration and Repair Swarup Bhunia and Rahul Rao
Analog Signature
2010

Technology-circuit co-design of asymmetric sram cells for read stability improvement
Jae-Joon Kim, Rahul Rao, Keunwoo Kim
Custom Integrated Circuits Conference (CICC), 2010 IEEE, pp. 1--4


2009

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation
Amlan Ghosh, Rahul M Rao, Richard B Brown
Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, pp. 45--50

A precise negative bias temperature instability sensor using slew-rate monitor circuitry
Amlan Ghosh, Richard B Brown, Rahul M Rao, Ching-Te Chuang
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp. 381--384

On-chip negative bias temperature instability sensor using slew rate monitoring circuitry
Amlan Ghosh, Rahul M Rao, Richard B Brown, Ching-Te Chuang
ACM IEEE Intl. Symposium on Low Power Electronics and Design, 2009

Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance
Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi Zafar, James H Stathis, Ching-Te Chuang
Reliability Physics Symposium, 2009 IEEE International, pp. 745--749

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi Zafar, James H Stathis, Ching-Te Chuang
Microelectronics reliability 49(6), 642--649, Pergamon, 2009

Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors
Jae-Joon Kim, Aditya Bansal, Rahul Rao, Shih-Hsien Lo, Ching-Te Chuang
IEEE Electron Device Letters 30(8), 852--854, IEEE, 2009

A local random variability detector with complete digital on-chip measurement circuitry
Rahul Rao, Keith A Jenkins, Jae-Joon Kim
IEEE Journal of Solid-State Circuits 44(9), 2616--2623, IEEE, 2009


2008

On-chip process variation detection using slew-rate monitoring circuit
Amlan Ghosh, Rahul M Rao, Jae-joon Kim, Ching-Te Chuang, Richard B Brown
VLSI Design, 2008. VLSID 2008. 21st International Conference on, pp. 143--149

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies
Saibal Mukhopadhyay, R Rao, Jae-Joon Kim, Ching-Te Chuang
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, pp. 384--387

On-chip process variation detection and compensation using delay and slew-rate monitoring circuits
Amlan Ghosh, Rahul M Rao, Ching-Te Chuang, Richard B Brown
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, pp. 815--820

Variability and power management in sub-100nm SOI technology for reliable high performance systems
Koushik Das, Kerry Bernstein, Jeff Burns, Fadi Gebara, Shih-Hsien Lo, Kevin Nowka, Rahul Rao, Michael Rosenfield
SOI Conference, 2008. SOI. IEEE International, pp. 1--4

Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects
Jae-Joon Kim, Rahul Rao, Saibal Mukhopadhyay, Ching-Te Chuang
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on, pp. 163--166

A completely digital on-chip circuit for local-random-variability measurement
Rahul Rao, Keith A Jenkins, Jae-Joon Kim
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 412--623


2007

On-chip process variation detection and compensation for parametric yield enhancement in sub-100nm CMOS technology
Amlan Ghosh, R Rao, R Brown, C Chuang
IBM Austin Center for Advanced Studies, 2007

Evaluation and Optimization of FinFET Quantization Error in Porting a Design from Planar Silicon Technology
R Rao, J Kim, CT Chuang
SOI Conference, 2007 IEEE International, pp. 49--50

Accurate modeling and analysis of currents in trapezoidal FinFET devices
R Rao, A Bansal, J Kim, K Roy, CT Chuang
SOI Conference, 2007 IEEE International, pp. 47--48

High-performance SRAM in nanoscale CMOS: Design challenges and techniques
Ching-Te Chuang, Saibal Mukhopadhyay, Jae-Joon Kim, Keunwoo Kim, Rahul Rao
Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on, pp. 4--12

Parametric yield analysis and optimization in leakage dominated technologies
Kanak Agarwal, Rahul Rao, Dennis Sylvester, Richard Brown
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(6), 613--623, IEEE, 2007


2005

Power-aware global signaling strategies
Dennis Sylvester, Himanshu Kaul, Kanak Agarwal, Rahul M Rao, Sani Nassif, Richard B Brown
IEEE International Symposium on Circuits and Systems, pp. 604, 2005

Silicon-on-insulator MOSFETs with hybrid crystal orientations
Min Yang, K Chan, A Kumar, S-H Lo, J Sleight, L Chang, R Rao, S Bedell, A Ray, J Ott, others
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 2005

Parametric yield analysis and constrained-based supply voltage optimization
Rahul Rao, Kanak Agarwal, Anirudh Devgan, Kevin Nowka, Dennis Sylvester, Richard Brown
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, pp. 284--290

Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization
Harmander Singh Deogun, Rahul Rao, Dennis Sylvester, Richard Brown, Kevin Nowka
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, pp. 88--93

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength
H Singh Deogun, Dennis Sylvester, R Rao, Kevin Nowka
SOC Conference, 2005. Proceedings. IEEE International, pp. 147--150


2004

Analysis and mitigation of CMOS gate leakage
Rahul M Rao, Richard B Brown, Kevin Nowka, Jeffrey L Burns
Proceedings of the Fifth Annual Austin Center for Advanced Studies Conference, pp. 7--11, 2004

Digital circuit design techniques for low-leakage silicon-on-insulator (SOI) CMOS technology.
Rahul M Rao
Ph.D. Thesis, 2004

Analysis and optimization of enhanced MTCMOS scheme
Rahul M Rao, Jeffrey L Burns, Richard B Brown
VLSI Design, 2004. Proceedings. 17th International Conference on, pp. 234--239

Approaches to run-time and standby mode leakage reduction in global buses
Rahul Rao, Kanak Agarwal, Dennis Sylvester, Richard Brown, Kevin Nowka, Sani Nassif
Proceedings of the 2004 international symposium on Low power electronics and design, pp. 188--193


2003

Efficient techniques for gate leakage estimation
Rahul M Rao, Jeffrey L Burns, Anirudh Devgan, Richard B Brown
Proceedings of the 2003 international symposium on Low power electronics and design, pp. 100--103

A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits
Rahul M Rao, Frank Liu, Jeffrey L Burns, Richard B Brown
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, pp. 689

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies
Rahul M Rao, Jeffrey L Burns, Richard B Brown
Solid-State Circuits Conference, 2003. ESSCIRC'03. Proceedings of the 29th European, pp. 313--316


Year Unknown

Mobile Computing and IBM POWER7+ Technologies
JJ Ritsko, V Zyuban, SA Taylor, B Christensen, AR Hall, CJ Gonzalez, J Friedrich, F Clougherty, J Tetzloff, R Rao, others
0

Dual Issue Power PC FXU
Jayakumaran Sivagnaname, Rahul Rao, Richard B Brown
0

Design of Deep Sub-Micron CMOS Circuits and Design Methodologies for High Performance Microprocessor
Ruchir Puri, Charudhattan Nagarajan, Sourav Saha, IBM Sridhar Rangarajan, Rahul Rao, Puneet Gupta
0

High Performance Design and Methodology in a 3D Integration Process
Ivan Vo, Tuyet Nguyen, Fadi Gebara, Jeremy Schaub, Rahul Rao, Jente B Kuang, Gary Carpenter, Kevin Nowka
0

Low-Leakage Robust Circuit Design
Rahul Rao, Richard Brown
0

E3 239 Advanced VLSI Circuits High-Performance SRAM Design
Rahul Rao
0