Rahul M Rao 
contact information
Senior Technical Staff Memer, Enterprise Systems DevelopmentBangalore, India +91
8040661261
8040661261 links
2016
Formal verification driven power modeling and design verification
Haridass, Anand and Joseph, Arun and Nalla, Pradeep Kumar and Rao, Rahul M
US Patent 9,460,251
Abstract
Haridass, Anand and Joseph, Arun and Nalla, Pradeep Kumar and Rao, Rahul M
US Patent 9,460,251
Abstract
Addressing early mode slack fails by book decomposition
Madiraju, Mithula and Rao, Rahul M
US Patent 9,519,746
Abstract
Madiraju, Mithula and Rao, Rahul M
US Patent 9,519,746
Abstract
Modified standard cells to address fast paths
Lewis, Daniel and Rao, Rahul M and Subramanya, Adarsh
US Patent 9,280,630
Abstract
Lewis, Daniel and Rao, Rahul M and Subramanya, Adarsh
US Patent 9,280,630
Abstract
2015
Estimating delay deterioration due to device degradation in integrated circuits
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent 8,966,420
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent 8,966,420
2013
Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)
Jae-Joon Kim, Rahul M Rao
US Patent 8,456,247
Jae-Joon Kim, Rahul M Rao
US Patent 8,456,247
Usage-based temporal degradation estimation for memory elements
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent App. 13/613,220
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent App. 13/613,220
Performing logic functions on more than one memory cell within an array of memory cells
Jente B Kuang, Rahul M Rao
US Patent 8,493,774
Jente B Kuang, Rahul M Rao
US Patent 8,493,774
2012
Dual-cell mtj structure with individual access and logical combination ability
Jae-Joon Kim, Rahul M Rao
US Patent App. 13/435,000
Jae-Joon Kim, Rahul M Rao
US Patent App. 13/435,000
On-Chip Delay Measurement Through a Transistor Array
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent App. 13/601,122
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent App. 13/601,122
Enhanced static random access memory stability using asymmetric access transistors and design structure for same
Aditya Bansal, Ching-Te K Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M Rao
US Patent 8,139,400
Aditya Bansal, Ching-Te K Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M Rao
US Patent 8,139,400
2011
Static pulsed bus circuit and method having dynamic power supply rail selection
Harmander Singh Deogun, Kevin J Nowka, Rahul M Rao, Robert M Senger
US Patent 7,882,370
Harmander Singh Deogun, Kevin J Nowka, Rahul M Rao, Robert M Senger
US Patent 7,882,370
Electronic circuit for measurement of transistor variability and the like
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent 8,004,305
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent 8,004,305
2010
Memory circuit with decoupled read and write bit lines and improved write stability
Rajiv V Joshi, Jae-Joon Kim, Rahul M Rao
US Patent 7,746,709
Rajiv V Joshi, Jae-Joon Kim, Rahul M Rao
US Patent 7,746,709
Methods of operating an electronic circuit for measurement of transistor variability and the like
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent 7,764,080
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent 7,764,080
Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect
Ching-Te K Chuang, Jae-Joon Kim, Tae-Hyoung Kim, Pong-Fei Lu, Saibal Mukhopadhyay, Rahul M Rao, Shao-yi Wang
US Patent 7,642,864
Ching-Te K Chuang, Jae-Joon Kim, Tae-Hyoung Kim, Pong-Fei Lu, Saibal Mukhopadhyay, Rahul M Rao, Shao-yi Wang
US Patent 7,642,864
2009
Techniques for improving write stability of memory with decoupled read and write bit lines
Rajiv V Joshi, Jae-Joon Kim, Rahul M Rao
US Patent 7,495,969
Rajiv V Joshi, Jae-Joon Kim, Rahul M Rao
US Patent 7,495,969
Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks
Dhruva J Acharyya, Sani R Nassif, Rahul M Rao
US Patent 7,550,987
Dhruva J Acharyya, Sani R Nassif, Rahul M Rao
US Patent 7,550,987
2006
FINFET drive strength de-quantization using multiple orientation fins
Jae-Joon Kim, Rahul M Rao
US Patent App. 11/505,224
Jae-Joon Kim, Rahul M Rao
US Patent App. 11/505,224
Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching
Harmander Singh Deogun, Kevin John Nowka, Rahul M Rao
US Patent 7,088,141
Harmander Singh Deogun, Kevin John Nowka, Rahul M Rao
US Patent 7,088,141
2004
Technique for mitigating gate leakage during a sleep state
Elad Alon, Jeffrey L Burns, Kevin J Nowka, Rahul M Rao
US Patent 6,791,361
Elad Alon, Jeffrey L Burns, Kevin J Nowka, Rahul M Rao
US Patent 6,791,361