Rahul M Rao  Rahul M Rao photo         

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Senior Technical Staff Memer, Enterprise Systems Development
Bangalore, India
  +91dash80dash406dash61261

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Professional Associations

Professional Associations:  ACM  |  IEEE Member


2018

Delayed equivalence identification
Raj Kumar Gajavelly, Ashutosh Misra, Pradeep Kumar Nalla, Rahul M Rao
US Patent 9,934,873

On the fly netlist compression in power analysis
Arun Joseph, Rahul M Rao
US Patent 9,996,649


2017

Formal verification driven power modeling and design verification
Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M Rao
US Patent App. 15/041,068

Cross-current power modelling using logic simulation
Arun Joseph, Arya Madhusoodanan, Rahul M Rao, Suriya T Skariah
US Patent App. 15/676,162


2016

Formal verification driven power modeling and design verification
Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M Rao
US Patent 9,460,251


2015

Usage-based temporal degradation estimation for memory elements
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent 9,058,448

Estimating delay deterioration due to device degradation in integrated circuits
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent 8,966,420

Usage-based temporal degradation estimation for memory elements
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent 9,058,448

Usage-based temporal degradation estimation for memory elements
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent 9,064,071


2013

On-Chip Delay Measurement Through a Transistor Array
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent App. 13/601,122

Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)
Jae-Joon Kim, Rahul M Rao
US Patent 8,456,247

Dual-cell mtj structure with individual access and logical combination ability
Jae-Joon Kim, Rahul M Rao
US Patent App. 13/435,000

Performing logic functions on more than one memory cell within an array of memory cells
Jente B Kuang, Rahul M Rao
US Patent 8,493,774

Enhanced static random access memory stability using asymmetric access transistors and design structure for same
Aditya Bansal, Ching-Te K Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M Rao
US Patent 8,526,219

Estimating delay deterioration due to device degradation in integrated circuits
Aditya Bansal, Jae-Joon Kim, Rahul M Rao
US Patent App. 13/428,571


2012

Enhanced static random access memory stability using asymmetric access transistors and design structure for same
Aditya Bansal, Ching-Te K Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M Rao
US Patent 8,139,400

On-Chip Delay Measurement Through a Transistor Array
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent App. 12/894,334


2011

Electronic circuit for measurement of transistor variability and the like
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent 8,004,305

Static pulsed bus circuit and method having dynamic power supply rail selection
Harmander Singh Deogun, Kevin J Nowka, Rahul M Rao, Robert M Senger
US Patent 7,882,370


2010

Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect
Ching-Te K Chuang, Jae-Joon Kim, Tae-Hyoung Kim, Pong-Fei Lu, Saibal Mukhopadhyay, Rahul M Rao, Shao-yi Wang
US Patent 7,642,864

Methods of operating an electronic circuit for measurement of transistor variability and the like
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent 7,764,080

Memory circuit with decoupled read and write bit lines and improved write stability
Rajiv V Joshi, Jae-Joon Kim, Rahul M Rao
US Patent 7,746,709


2009

Apparatus and method for determining the slew rate of a signal produced by an integrated circuit
Ching-Te K Chuang, Amlan Ghosh, Jae-Joon Kim, Rahul M Rao
US Patent 7,548,822

Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks
Dhruva J Acharyya, Sani R Nassif, Rahul M Rao
US Patent 7,550,987

Techniques for improving write stability of memory with decoupled read and write bit lines
Rajiv V Joshi, Jae-Joon Kim, Rahul M Rao
US Patent 7,495,969


2008

Electronic circuit for measurement of transistor variability and the like
Keith A Jenkins, Jae-Joon Kim, Rahul M Rao
US Patent 7,439,755

FINFET drive strength de-quantization using multiple orientation fins
Jae-Joon Kim, Rahul M Rao
US Patent App. 11/505,224


2006

Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching
Harmander Singh Deogun, Kevin John Nowka, Rahul M Rao
US Patent 7,088,141


2004

Technique for mitigating gate leakage during a sleep state
Elad Alon, Jeffrey L Burns, Kevin J Nowka, Rahul M Rao
US Patent 6,791,361