2022
Electrical charger with correction capability for wearable electrochemical sensor
Keiji Matsumoto, Takahito Watanabe, Eiji Nakamura, Patrick Ruch, Hiroyuki Mori
Abstract
To be filed
2019
Battery embedded architecture for supplying appropriate voltage
K Matsumoto, H Mori
Abstract
A battery embedded structure is disclosed. The battery embedded structure comprises a substrate including one or more stacked battery units. Each stacked battery unit includes two or more conductive layers and one or more unit cells. Each unit cell is disposed between two conductive layers. The substrate has a principal surface provided by one or more respective side surfaces of the one or more stacked battery units. The battery embedded structure also comprises a wiring layer disposed on the principal surface of the substrate. The wiring layer includes a plurality of electrical paths and a plurality of vias. Each via is connected with one electrical path. Each via is located at a position corresponding to an edge surface of a conductive layer of the two or more conductive layers of the one or more stacked battery units so as to contact electrically to that conductive layer.
2018
Electrical connecting structure between a substrate and a semiconductor chip
K Matsumoto, K Okamoto, YK Orii, K Toriyama
Abstract
The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.
Chip mounting structure
Akihiro Horibe, Keiji Matsumoto, Keishi Okamoto, Kazushige Toriyama
Abstract
Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.
2017
Method, apparatus, and structure for determining interposer thickness
S Hada, A Horibe, K Matsumoto
Abstract
The present invention includes the following steps: setting the thickness of an interposer to an initial value; determining the axial force of the interposer and the radius of curvature of the warpage caused by the difference in the thermal expansion coefficients of the supporting substrate, the joined layer and the interposer at the set thickness; determining the absolute value of the stress on the chip-connecting surface of the interposer from the stress due to the axial force of the interposer and the stress due to the warpage using the determined axial force and the radius of curvature; determining whether or not the absolute value of the stress is within a tolerance; changing the thickness of the interposer by a predetermined value; and confirming the set thickness as the thickness of the interposer when the determined absolute value of the stress is within the tolerance.
Electrical package including bimetal lid
K Matsumoto, H Mori
Abstract
Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM,(ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.
2016
Substrate device and electric circuit arrangement having first substrate section perpendicular to second substrate section
Thomas J Brunschwiler, Dominic Gschwend, Keiji Matsumoto, Stefano S Oggioni, Gerd Schlottig, Timo J Tick, Jonas Zuercher
Abstract
A substrate device for electronic circuits or devices includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are angled (??) with respect to one another.
2014
Reduction of warpage of multilayered substrate or package
Sayuri Hada, Keiji Matsumoto
Abstract
A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, ????, varies in a substrate. The method focuses in on the difference in ???? with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in ???? with a smaller length scale (high frequency) and corrects only the difference in ???? with a greater length scale. The distribution of the difference in ???? in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in ???? with a low frequency and the difference in ???? between before and after correction, thereby revealing a part that requires correction.
2013
Surface region selection for heat sink placement
Keiji Matsumoto
Abstract
A method for determining an area of a region for receiving a heat sink on a surface of a chip-supporting substrate is disclosed. The method can include determining, in response to a specified voltage drop associated with substrate wiring, a first set of wiring cross-sectional areas and corresponding lengths that satisfy the specified voltage drop. The method can also include determining, by selecting, in response to a specified thermal resistance associated with substrate wiring and insulating layers, from the first set, a second set of wiring cross-sect...
Achieving power supply and heat dissipation (cooling) in three-dimensional multilayer package
Keiji Matsumoto
Abstract
A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatuses include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.
2008
UNDERFILL FILM HAVING THERMALLY CONDUCTIVE SHEET
Keiji Matsumoto
Abstract
An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board.
2005
THREE LEVEL STACKED REFLECTIVE DISPLAY DEVICE
Keiji Matsumoto, Lubomyr T. Romankiw, Kuniaki Sueoka, Yoichi Taira, Keizoh Takeda
Abstract
A structure and fabrication technology for a reflective, ambient light, low cost display is described incorporating a plurality of cells laid out side by side and stacked as many as three levels on top of each other. Each stack of three cells being driven by an array of TFT's positioned on the bottom layer. Each cell comprises a light transmitting front window, three levels of individual cells RGB (Red, Green, and Blue) stacked on top of each other, each level having its own individual electrode, each electrode being connected by vertical conducting via holes running through each transparent dielectric spacert and being connected to a individual TFT. The bottom panel having a reflective surface so as to provide maximum reflectivity of the ambient light. Placed under the reflective surface is an array of TFT's which provide the electrical impulses necessary to set each individual potential in each vertically stacked cell with respect to ground potential. A transmissive liquid crystal display can readily be fabricated by deleting the reflective surface. Also described are structures and assembly methods suitable for fabricating a Guest-Host LCD, a Cholesteric LCD, a Holographic Polymer Dispersed LCD and an Organic Light Emitting Diode (OLED) display.
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