Atsushi Matsuo  Atsushi Matsuo photo         

contact information

Researcher
Tokyo Research Laboratory, Yamato, Japan
  +81dash50dash3150dash1885

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2021

Engrossed in Quantum Technology: Quantum Virtual Hackathon - Raising Quantum Talents by the Community [Japanese]
Yuri Kobayashi, Atsushi Matsuo, Kifumi Numata
Information Processing magazine 62(4), 53-58, Information Processing Society of Japan, 2021

Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization
Yudai Suzuki Atsushi Matsuo, Shigeru Yamashita
2021 20th Asian Quantum Information Science Conference (AQIS), pp. 161-161

Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures
A. Matsuo, W. Hattori, S. Yamashita
2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 786-791


2020

Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization Problems
Atsushi Matsuo, Yudai Suzuki, Shigeru Yamashita
2020

Optimization of quantum circuit mapping using gate transformation and commutation
Toshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo
Integration70, 43-50, 2020
Abstract


2019

An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid
Atsushi Matsuo, Shigeru Yamashita
Reversible Computation, pp. 162--168, Springer International Publishing, 2019
Abstract

Reducing the Overhead of Mapping Quantum Circuits to IBM Q System
A. Matsuo, W. Hattori, S. Yamashita
2019 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5

Quantum Circuit Compilers Using Gate Commutation Rules
Toshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo, Andrew W. Cross
Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 191–196, Association for Computing Machinery, 2019
Abstract

Quantum Circuit Compilers Using Gate Commutation Rules
Toshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo, Andrew W. Cross
Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 191–196, Association for Computing Machinery, 2019
Abstract


2018

Quantum circuit synthesis and optimization [Japanese]
Shigeru Yamashita, Atsushi Matsuo
Operations Research Magazine 63(6), 342-349, Operations Research Society of Japan, 2018


2013

Fault-Tolerant Design with Less Overhead than DMR
Atsushi Matsuo, Shigeru Yamashita
IEICE Technical Report; IEICE Tech. Rep. 113(320), 33--37, IEICE, 2013


2012

Changing the Gate Order for Optimal LNN Conversion
Atsushi Matsuo, Shigeru Yamashita
Reversible Computation, pp. 89--101, Springer Berlin Heidelberg, 2012
Abstract