Takuya Nakaike  Takuya Nakaike photo         

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Research Staff Member - Performance Analysis and Optimization
IBM Research - Tokyo



Hyperledger Fabric Performance Characterization and Optimization Using GoLevelDB Benchmark
Takuya Nakaike, Qi Zhang, Yohei Ueda, Tatsushi Inagaki, Moriyoshi Ohara
2020 IEEE International Conference on Blockchain and Cryptocurrency (ICBC), 1-9
Abstract   transactions per second, ledger, database transaction, database access, database, data compression, computer science, bottleneck, blockchain, benchmark


Profile-based Detection of Layered Bottlenecks
Tatsushi Inagaki, Yohei Ueda, Takuya Nakaike, Moriyoshi Ohara
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, ICPE 2019, Mumbai, India, April 7-11, 2019., pp. 197--208, ACM


Workload Characterization for Microservices
Takanori Ueda, Takuya Nakaike, Moriyoshi Ohara
2016 IEEE International Symposium on Workload Characterization, IISWC 2016, Providence, RI, USA, September 25-27, 2016, pp. 85--94


Quantitative Comparison of Hardware Transactional Memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8
Takuya Nakaike, Rei Odaira, Matthew Gaudet, Maged M. Michael, and Hisanobu Tomari
roceedings of the 42nd International Symposium on Computer Architecture (ISCA), pp. 144-157, 2015

Transactional memory support in the IBM POWER8 processor
HQ Le, GL Guthrie, DE Williams, MM Michael, BG Frey, WJ Starke, C May, R Odaira, T Nakaike
IBM Journal of Research and Development 59(1), 8--1, IBM, 2015


Characterization of Call-Graph Profiles in Java Workloads
Takuya Nakaike, Hiroshi Inoue, Toshio Suganuma, Moriyoshi Ohara
Proceedings of the IEEE International Symposium on Workload Characterization (IISWC 2014), IEEE, pp. 85--102

Thread-Level Speculation on Off-the-Shelf Hardware Transactional Memory
Rei Odaira and Takuya Nakaike
Proceedings of the 2014 IEEE International Symposium on Workload Characterization (IISWC), pp. 212--221


Do C and Java programs scale differently on Hardware Transactional Memory
Rei Odaira, Jose G. Castanos, Takuya Nakaike
2013 IEEE International Symposium on Workload Characterization (IISWC), pp. 34-43
Abstract   real time java, java concurrency, java annotation, strictfp, java, transactional memory, java card, embedded java, operating system, programming language, computer science

Do C and Java Programs Scale Differently on Hardware Transactional Memory?
Rei Odaira, Jose G. Castanos, and Takuya Nakaike
Proceedings of the 2013 IEEE International Symposium on Workload Characterization (IISWC), pp. 34--43


Real Java Applications in Software Transactional Memory
Takuya Nakaike, Rei Odaira, Toshio Nakatani, and Maged M. Michael
Proceedings of the 2010 IEEE International Symposium on Workload Characterization (IISWC), pp. 1--10

Coloring-based Coalescing for Graph Coloring Register Allocation
Rei Odaira, Takuya Nakaike, Tatsushi Inagaki, Hideai Komatsu, and Toshio Nakatani
Proceedings of the 8th annual IEEE/ACM international Symposium on Code Generation and Optimization (CGO), pp. 160--169, 2010

Lock elision for read-only critical sections in Java
Takuya Nakaike, Maged M Michael
ACM SIGPLAN Notices 45(6), 269--278, ACM, 2010


Reducing Rollbacks of Transactional Memory Using Ordered Shared Locks
Ken Mizuno, Takuya Nakaike, Toshio Nakatani
Euro-Par 2009 Parallel Processing, pp. 704--715, Springer


Compiler and Runtime Techniques for Software Transactional Memory Optimization
Peng Wu, Maged M. Michael, Christoph Von Praun, Takuya Nakaike, Rajesh Bordawekar, Harold W. Cain, Gheorghe Cascaval, Siddhartha Chatterjee, Stefanie R. Chiras, Rui Hou, Mark F. Mergen, Xiaowei Shen, Hua Yong Wang, Kun Wang and Michael Spear
Concurrency and Computation: Practice and Experience 21(1), 7--23, John Wiley & Sons, 2008


Profile-based global live-range splitting
Takuya Nakaike, Tatsushi Inagaki, Hideaki Komatsu, Toshio Nakatani
PLDI '06 Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation , pp. 216--227, Google Patents
US Patent 8,555,270


JSP splitting for improving execution performance
Takuya Nakaike, Goh Kondoh, Hiroaki Nakamura, Fumihiko Kitayama, Shinichi Hirose
Applications and the Internet, 2004. Proceedings. 2004 International Symposium on, pp. 117--126


Design and Evaluation of the MULHI Cache
Jubei TADA, Takuya NAKAIKE, Ken-ichi SUZUKI, Nobuyuki OOBA, Hiroaki KOBAYASHI, Tadao NAKAMURA
IEICE transactions on information and systems 85(3), 597, 一般社団法人電子情報通信学会, 2002


Memory hierarchy design for Jetpipeline: to execute scalar and vector instructions in parallel
Takehito Sasaki, Takuya Nakaike, Koji Takano, Masayuki Katahira, Hiroaki Kobayashi, Tadao Nakamura
Parallel Algorithms/Architecture Synthesis, 1997. Proceedings., Second Aizu International Symposium, pp. 66--73