Robert H. Dennard  Robert H. Dennard photo         

contact information

IBM Fellow
Thomas J. Watson Research Center, Yorktown Heights, NY USA



A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2
Chang, Leland; Montoye, R.K.; Ji, B.L.; Weger, A.J.; Stawiasz, K.G.; Dennard, R.H.;
2010 IEEE Symposium on VLSI Circuits (VLSIC), pp. 55--56


Thanks for the Memories
A R Dennard
2009 -


Revisiting “Evolution of the MOSFET Dynamic RAM--A Personal View”
R H Dennard
Solid-State Circuits Newsletter, IEEE 13(1), 10--16, IEEE, 2008

Dennard Receives Medal from Benjamin Franklin Institute
B Scheraga
Solid-State Circuits Newsletter, IEEE 13(2), 25--25, IEEE, 2008

The History of DRAM Circuit Designs--At the Forefront of DRAM Development--
K Itoh
Solid-State Circuits Newsletter, IEEE 13(1), 27--31, IEEE, 2008


Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions
Solid-State Circuits Newsletter, IEEE 12(1), 38--50, IEEE, 2007

A 30 year retrospective on Dennard’s MOSFET scaling paper
M Bohr
IEEE SSCS Newsletter 12(1), 11--13, 2007

A perspective on today’s scaling challenges and possible future directions
R H Dennard, J Cai, A Kumar
Solid-State Electronics 51(4), 518--525, Elsevier, 2007


A 3-transistor DRAM cell with gated diode for enhanced speed and retention time
W K Luk, J Cai, R H Dennard, M J Immediato, S V Kosonocky
VLSI Circuits, 2006, pp. 184--185


A novel dynamic memory cell with internal voltage gain
W K Luk, R H Dennard
Solid-State Circuits, IEEE Journal of 40(4), 884--894, IEEE, 2005


2T1D memory cell with voltage gain
W K Luk, R H Dennard
VLSI Circuits, 2004, pp. 184--187


Supply voltage strategies for minimizing the power of CMOS processors
J Cai, Y Taur, S F Huang, D J Frank, S Kosonocky, R H Dennard
VLSI Technology, 2002, pp. 102--103

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
J A Mandelman, R H Dennard, G B Bronner, J K DeBrosse, R Divakaruni, Y Li, C J Radens
IBM Journal of Research and Development 46(2.3), 187--212, IBM, 2002


Scalability and biasing strategy for CMOS with active well bias
S F Huang, C Wann, Y S Huang, C Y Lin, T Schafbauer, S M Cheng, Y C Cheng, D Vietzke, M Eller, C Lin, others
VLSI Technology, 2001, pp. 107--108

Device scaling limits of Si MOSFETs and their application dependencies
D J Frank, R H Dennard, E Nowak, P M Solomon, Y Taur, H S P Wong
Proceedings of the IEEE 89(3), 259--288, IEEE, 2001


Creativity in the 2000s and beyond
R H Dennard
Research Technology Management 43(6), 23--25, Proquest ABI/INFORM, 2000

Theoretical determination of the temporal and spatial structure of $\alpha$-particle induced electron-hole pair generation in silicon
P Oldiges, R Dennard, D Heidel, B Klaasen, F Assaderaghi, M Ieong
Nuclear Science, IEEE Transactions on 47(6), 2575--2579, IEEE, 2000

1-GHz fully pipelined 3.7-ns address access time 8 k$\times$ 1024 embedded synchronous DRAM macro
O Takahashi, S H Dhong, M Ohkubo, S Onishi, R H Dennard, R Hannon, S Crowder, S S Iyer, M R Wordeman, B Davari, others
Solid-State Circuits, IEEE Journal of 35(11), 1673--1679, IEEE, 2000


Design of ion-implanted MOSFET's with very small physical dimensions
R H Dennard, F H Gaensslen, H N Yu, V L Rideout, E Bassous, A R LeBlanc
Proceedings of the IEEE 87(4), 668--678, 1999


Scaling challenges for DRAM and microprocessors in the 21st century
R H Dennard
Electrochemical Society Proceedings, pp. 3, 1997


Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET
C Wann, F Assaderaghi, R Dennard, C Hu, G Shahidi, Y Taur
Electron Devices Meeting, 1996, pp. 113--116


CMOS scaling for high performance and low power-the next ten years
B Davari, R H Dennard, G G Shahidi
Proceedings of the IEEE 83(4), 595--606, IEEE, 1995


CMOS technology for low voltage/low power applications
B Davari, R H Dennard, G G Shahidi
Custom Integrated Circuits Conference, 1994, pp. 3--10


Submicrometer-channel CMOS for low-temperature operation
J Y C Sun, Y Taur, R H Dennard, S P Klepner
Electron Devices, IEEE Transactions on 34(1), 19--27, IEEE, 1987


MOSFET miniaturization--From one micron to the limits
R H Dennard, M R Wordeman
Physica B+ C 129(1-3), 3--15, Elsevier, 1985


Evolution of the MOSFET dynamic RAM—a personal view
R H Dennard
Electron Devices, IEEE Transactions on 31(11), 1549--1555, IEEE, 1984



IBM Thomas J. Watson Research Center Yorktown Heights, NY 10598
R H Dennard
Large scale integrated circuits technology: state of the art and prospects: proceedings of the NATO Advanced Study Institute on" Large Scale Integrated Circuits Technology: State of the Art and Prospects," Erice, Italy, July 15-27, 1981, pp. 487, 1982


Threshold voltage characteristics of depletion-mode MOSFET's
M R Wordeman, R H Dennard
Electron Devices, IEEE Transactions on 28(9), 1025--1030, IEEE, 1981


Design of ion-implanted MOSFET's with very small physical dimensions
R H Dennard, F H Gaensslen, VL Rideout, E Bassous, AR LeBlanc
Solid-State Circuits, IEEE Journal of 9(5), 256--268, IEEE, 1974


Design of micron MOS switching devices
R H Dennard, F H Gaensslen, L Kuhn, HN Yu
Electron Devices Meeting, 1972 International, pp. 168--170

Year Unknown