David J. Frank  David J. Frank photo         

contact information

CMOS and novel device and circuit exploration
Thomas J. Watson Research Center, Yorktown Heights, NY USA


Professional Associations

Professional Associations:  IEEE Electron Devices Society (EDS)


Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation
B L Ji, D J Pearson, I Lauer, F Stellari, D J Frank, L Chang, M B Ketchen

Increasing Threshold Voltage Variation due to Random Telegraph Noise in FETs as Gate Lengths Scale to 20 nm
N Tega, H Miki, F Pagette, DJ Frank, A Ray, MJ Rooks, W Haensch, K Torii
VLSI Symp., pp. 50-1, 2009


Upside-down FETS
DC La Tulipe, DJ Frank, SE Steen, AW Topol, J Patel, L Ramakrishnan, JW Sleight
IEEE International SOI Conference, 2008, pp. 23--24

Connection device with actuating element for changing a conductive state of a via
D J Frank, K W Guarini, C B Murray, X Wang, H S P Wong
US Patent ..., 2008 - Google Patents, Google Patents
US Patent 7,342,301


High performance CMOS variability in the 65nm regime and beyond
S Nassif, K Bernstein, DJ Frank, A Gattiker, W Haensch, BL Ji, E Nowak, D Pearson, NJ Rohrer
IEEE International Electron Devices Meeting, pp. 569--571, 2007

Overlay as the key to drive wafer scale 3D integration
S E Steen, D LaTulipe, A W Topol, D J Frank, K Belote, D Posillico
Microelectronic Engineering 84(5-8), 1412--1415, Elsevier, 2007

35nm SOI-CMOS for Sub-Ambient Temperature Operation
J Cai, DJ Frank, H Yin, RH Dennard, WE Haensch
VLSI Technology, Systems and Applications, 2007, pp. 1--2


High-performance CMOS variability in the 65-nm regime and beyond
K Bernstein, DJ Frank, AE Gattiker, W Haensch, BL Ji, SR Nassif, EJ Nowak, DJ Pearson, NJ Rohrer
IBM Journal of Research and Development 50(4/5), 449, IBM Corp., 2006

Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design
S Mukhopadhyay, K Kim, X Wang, D J Frank, P Oldiges, C Chuang, K Roy

Design and CAD challenges in 45nm CMOS and beyond
D J Frank, R Puri, D Toma
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp. 333

Wafer Scale 3-D Integration: Overlay as the Key to Drive Potential
S E Steen, DC La Tulipe, AW Topol, DJ Frank, K Belote, D Posillico
Microelectr. Eng84, 1412--1415, 2006

Optimizing CMOS technology for maximum performance
DJ Frank, W Haensch, G Shahidi, OH Dokumaci
IBM Journal of Research and Development 50(4/5), 431, IBM Corp., 2006

Practical CMOS Scaling
D J Frank
Silicon nanoelectronics, pp. 33, CRC, 2006

Method of fabricating a connection device
D J Frank, K W Guarini, C B Murray, X Wang, H S P Wong
US Patent ..., 2006 - Google Patents, Google Patents
US Patent 7,074,707

Three-dimensional integrated circuits
A W T D C La Tulipe Jr, L S D J F K Bernstein, S E S A K G U Singco, A M Y K W G M Ieong
IBM Journal of Research and Development 50(4/5), 万方数据资源系统, 2006


Strained silicon-channel MOSFET using a damascene gate process
H I Hanafi, D J Frank, K K Chan
US Patent App. 11/113,858, 2005 - Google Patents, Google Patents
US Patent App. 11/113,858


Universal tunneling behavior in technologically relevant P/N junction diodes
P M Solomon, J Jopling, D J Frank, C D’Emic, O Dokumaci, P Ronsheim, WE Haensch
Journal of Applied Physics95, 5800, 2004

Parameter Variations in Sub-100nm MOS Technology
D J Frank
presentation at ISSCC2004 Microprocessor Design Forum

High-frequency response in carbon nanotube field-effect transistors
DJ Frank, J Appenzeller
IEEE Electron Device Letters 25(1), 34--36, 2004

Aggressively scaled (0.143 $\mu$m 2) 6T-SRAM cell for the 32 nm node and beyond
DM Fried, JM Hergenrother, AW Topol, L Chang, L Sekaric, JW Sleight, SJ McNab, J Newbury, SE Steen, G Gibson, others
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 261--264


Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits
A Bhavnagarwala, D J Frank, S V Kosonocky
US Patent App. 10/643,193, 2003 - Google Patents, Google Patents
US Patent App. 10/643,193

Growth and scaling of oxide conduction after breakdown
BP Linder, JH Stathis, DJ Frank, S Lombardo, A Vayshenker
2003 IEEE International Reliability Physics Symposium Proceedings, 2003, pp. 402--405


Power-constrained CMOS scaling limits
D J Frank
IBM Journal of Research and Development 46(2-3), 235--344, Citeseer, 2002

CMOS Device Technology Trends for Power Constrained Applications
D J Frank
Power Aware Design Methodologies, pp. 9-50, Springer, 2002

Design considerations for CMOS near the limits of scaling
D J Frank, Y Taur
Solid State Electronics 46(3), 315--320, Elsevier, 2002

Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics
BP Linder, S Lombardo, JH Stathis, A Vayshenker, DJ Frank
IEEE Electron Device Letters 23(11), 661--663, 2002

Electrical integrity of state-of-the-art 0.13/spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
KW Guarini, AW Topol, M Ieong, R Yu, L Shi, MR Newport, DJ Frank, DV Singh, GM Cohen, SV Nitta, others
Electron Devices Meeting, 2002, pp. 943--945

Method for increasing the capacitance of a semiconductor capacitors
S J Holmes, C Black, D J Frank, T Furukawa, M C Hakey, D V Horak, W H L Ma, K R Milkove, K W Guarini, others
US Patent ..., 2002 - Google Patents, Google Patents
US Patent 6,358,813

Supply voltage strategies for minimizing the power of CMOS processors
J Cai, Y Taur, S F Huang, D J Frank, S Kosonocky, R H Dennard
VLSI Technology, 2002, pp. 102--103


Device scaling limits of Si MOSFETs and their application dependencies
D J Frank, R H Dennard, E Nowak, P M Solomon, Y Taur, H S P Wong
Proceedings of the IEEE 89(3), 259--288, IEEE, 2001

Calculating the error in long term oxide reliability estimates
BP Linder, JH Stathis, DJ Frank
2001 IEEE International Reliability Physics Symposium, 2001, pp. 168--171

Transistor-limited constant voltage stress of gate dielectrics
BP Linder, DJ Frank, JH Stathis, SA Cohen
VLSI Technology, 2001, pp. 93--94


DC and AC performance analysis of 25 nm symmetric/asymmetricdouble-gate, back-gate and bulk CMOS
M K Ieong, H S P Wong, Y Taur, P Oldiges, D Frank, H J IBM SRDC
Simulation of Semiconductor Processes and Devices, 2000, pp. 147--150

Simulation of stochastic doping effects in Si MOSFETs
DJ Frank, H S P Wong
Computational Electronics, 2000, pp. 2--3


Nanoscale cmos
H S P Wong, D J Frank, P M Solomon, C H J Wann, J J Welser
Proceedings of the IEEE 87(4), 537--570, 1999

Monte Carlo modeling of threshold variation due to dopantfluctuations
DJ Frank, Y Taur, M Ieong, H S P Wong
VLSI Technology, 1999, pp. 169--170

Future prospects for Si CMOS technology
DJ Frank, Y Taur, H S P Wong
Device Research Conference Digest, 1999 57th Annual, pp. 18--21


RF perspective of sub-tenth-micron CMOS
C Wann, L Su, K Jenkins, R Chang, D Frank, Y Taur
1998 IEEE International Solid-State Circuits Conference, 1998, pp. 254--255

Discrete random dopant distribution effects in nanometer-scale MOSFETs
H S Philip Wong, Y Taur, D J Frank
Microelectronics Reliability 38(9), 1447--1456, Elsevier, 1998

Generalized scale length for two-dimensional effects in MOSFETs
DJ Frank, Y Taur, H S P Wong
IEEE Electron Device Letters 19(10), 385--387, 1998

25 nm CMOS design considerations
Y Taur, CH Wann, DJ Frank
Electron Devices Meeting, 1998, pp. 789--792


Application and technology forecast
D J Frank
Kluwer Nato Advanced Science Institutes Series, 9--44, Kluwer Academic Publishers Norwell, MA, USA, 1997

CMOS scaling into the nanometer regime
Y Taur, D A Buchanan, W Chen, D J Frank, K E Ismail, S H Lo, G A Sai-Halasz, R G Viswanathan, H J C Wann, S J Wind, others
Proceedings of the IEEE 85(4), 486--504, 1997

Supply and threshold voltage optimization for low power design
D J Frank, P Solomon, S Reynolds, J Shin
Proceedings of the 1997 international symposium on Low power electronics and design, pp. 317--322


Comparison of high speed voltage-scaled conventional and adiabatic circuits
D Frank
Proceedings of the 1996 international symposium on Low power electronics and design, pp. 380

Memory with adiabatically switched bit lines
R H Dennard, D J Frank
US Patent 5,526,319, 1996 - Google Patents, Google Patents
US Patent 5,526,319

Static combinatorial logic circuits for reversible computation
D J Frank
US Patent 5,493,240, 1996 - Google Patents, Google Patents
US Patent 5,493,240

CMOS toggle flip-flop using adiabatic switching
D J Frank
US Patent 5,517,145, 1996 - Google Patents, Google Patents
US Patent 5,517,145

Energy conserving clock pulse generating circuits
D J Frank, P M Solomon
US Patent 5,506,520, 1996 - Google Patents, Google Patents
US Patent 5,506,520

Probing the Limits of Silicon-Based Nanoelectronics
SJ Wind, Y Taur, Y Mii, DJ Frank, HS Wong, DA Buchanan, SA Rishton, JJ Bucchignano, Y Lii, KA Jenkins


CMOS Scaling into the 21 st Century: 0.1 $\mu$m and Beyond, IBMJ
Y Taur, YJ Mii, DJ Frank, HS Wong, DA Buchanan, SJ Wind, SA Rishton, GA Sai-Halasz, EJ Nowak
Res. Develop39, 245--259, 1995

Power measurements of adiabatic circuits by thermoelectrictechnique
PM Solomon, DJ Frank
IEEE Symposium on Low Power Electronics, 1995, pp. 18--19

Electroid-oriented adiabatic switching circuits
D J Frank, P M Solomon
Proceedings of the 1995 international symposium on Low power design, pp. 197--202


Design and performance considerations for sub-0.1 $\mu$m double-gateSOI MOSFET'S
H S Wong, DJ Frank, Y Taur, JMC Stork
Electron Devices Meeting, 1994, pp. 747--750

GaAS-Gate Semiconductor-Insulator-Semiconductor FET
P Solomon, D J Frank, S L Wright, F Canora
High Speed Heterostructure Devices: High Speed Heterostructure Devices, 79, Academic Press, 1994


Monte Carlo simulations of p-and n-channel dual-gate Si MOSFET'sat the limits of scaling
DJ Frank, SE Laux, MV Fischetti
IEEE Transactions on Electron Devices 40(11), 1993


Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?
DJ Frank, SE Laux, MV Fischetti
IEDM Tech. Dig553, Citeseer, 1992

Empiri, cal fit to band discsntinuities and barrier systems
S Tiwari, D J Frank
Appl. Phys. Lett 60(5), 1992


High-speed, low-voltage complementary heterostructure FET circuittechnology
RA Kiehl, J Yates, LF Palmateer, SL Wright, DJ Frank, TN Jackson, JF Degelormo, AJ Fleischman
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1991, pp. 101--104

Novel InAs/(Al, Ga) Sb FET with direct gate-to-channel contact
DJ Frank, DC La Tulipe Jr, H Munekata
IEEE Electron Device Letters 12(5), 210--212, 1991


Monte Carlo analysis of semiconductor devices: The DAMOCLES program
SE Laux, MV Fischetti, DJ Frank
IBM Journal of Research and Development 34(4), 466--494, IBM Corp. Riverton, NJ, USA, 1990

Superconductor-semiconductor hybrid transistors
DJ Frank
(International Conference on Low Temperature Electronics, 1st, Berkeley, CA, Apr, 1990

Heterojunction FETs in III-V compounds
RA Kiehl, PM Solomon, DJ Frank
IBM Journal of Research and Development 34(4), 506--529, IBM Corp. Riverton, NJ, USA, 1990

Compound semiconductor heterostructure bipolar transistors
S Tiwari, SL Wright, DJ Frank
IBM J. Res. Develop 34(4), 1990


Heterojunction bipolar transistor with substantially aligned energy levels
D J Frank, R F Marks
US Patent 4,821,082, 1989 - Google Patents, Google Patents
US Patent 4,821,082

Analysis of the operation of GaAlAs/GaAs HBTs
S Tiwari, DJ Frank
IEEE Transactions on Electron Devices 36(10), 2105--2121, 1989

New phenomena in coupled transport between 2D and 3D electron-gas layers
PM Solomon, PJ Price, DJ Frank, DC La Tulipe
Physical Review Letters 63(22), 2508--2511, APS, 1989

Noise model for the superconducting-base semiconductor-isolatedtransistor
A Davidson, DJ Frank
IEEE Transactions on Magnetics 25(2), 1278--1281, 1989


Surface recombination in GaAlAs/GaAs heterostructure bipolartransistors
S Tiwari, DJ Frank, SL Wright
IEEE Transactions on Electron Devices 35(12), 1988

Quasi-one-dimensional electron states in a split-gate GaAs/AlGaAs heterostructure
SE Laux, DJ Frank, F Stern
Surface Science 196(1-3), 101--106, Elsevier, 1988


Ion implantation and annealing of undoped (Al, Ga) As/GaAs heterostructures
H Baratte, TN Jackson, PM Solomon, DC LaTulipe, DJ Frank, JS Moore
Applied Physics Letters51, 1459, 1987

Device physics of quantum-well heterostructure MI 3 SFET's
RA Kiehl, DJ Frank, SL Wright, JH Magerlein
Electron Devices Meeting, 1987 International

Enhance/Deplete GaAs SISFETs
H Baratte, DC La Tulipe, DJ Frank, PM Solomon, TN Jackson, SL Wright
IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987, pp. 121--134

Electron interference effects in quantum wells: Observation of bound and resonant states
M Heiblum, MV Fischetti, WP Dumke, DJ Frank, IM Anderson, CM Knoedler, L Osterling
Physical review letters 58(8), 816--819, APS, 1987

Ion-Implanted Self-Aligned-Gate Quantum-well Heterostructure FETs
RA Kiehl, SL Wright, JH Magerlein, DJ Frank
IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987, pp. 144--153


Self-aligned processes for the GaAs gate FET
H Baratte, DC La Tulipe, CM Knoedler, TN Jackson, DJ Frank, PM Solomon, SL Wright
Electron Devices Meeting, 1986 International

Excess Gate Current Due to Hot Electrons in GaAs-Gate FETs
DJ Frank, PM Solomon, DC La Tulipe Jr, H Baratte, CM Knoedler, SL Wright
High-speed Electronics: Basic Physical Phenomena and Device Principles: Proceedings of the International Conference, Stockholm, Sweden, August 7-9, 1986, pp. 140

Cryogenic transistor with a superconducting base and a semiconductor-isolated collector
D J Frank
US Patent 4,575,741, 1986 - Google Patents, Google Patents
US Patent 4,575,741


Role of quasiparticle scattering in Gray’s superconducting transistor
DJ Frank, A Davidson, TM Klapwijk
Applied Physics Letters46, 603, 1985


A circuit-oriented quiteron analysis
D J Frank
Journal of Applied Physics56, 2553, 1984

Percolative conduction and the Alexander-Orbach conjecture in two dimensions
CJ Lobb, DJ Frank
Physical Review B 30(7), 4090--4092, APS, 1984


Transient response of superconducting indium microbridges to supercritical current pulses
DJ Frank, M Tinkham, A Davidson, SM Faris
Physical Review Letters 50(20), 1611--1614, APS, 1983


A large-cell renormalisation group calculation of the percolation conduction critical exponent
CJ Lobb, DJ Frank
Journal of Physics C: Solid State Physics12, L827--L830, Institute of Physics Publishing, 1979