Evelyn Duesterwald 
contact information
Principal Research Staff Member and Manager, Cognitive Systems Performance LabT. J. Watson Research Center, Hawthorne, NY USA +1
9147846422
9147846422 links
Professional Associations
Professional Associations: ACM Distinguished Scientist2014
Incorporating user insights into predicting, diagnosing and remediating problems that threaten on-time delivery of software and systems
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/184,285
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/184,285
Detecting patterns that increase the risk of late delivery of a software project
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/178,995
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/178,995
Gui support for diagnosing and remediating problems that threaten on-time delivery of software and systems
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/184,187
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/184,187
Interactive iterative program parallelization based on dynamic feedback
Evelyn Duesterwald, Robert M Fuhrer, Vijay Saraswat
US Patent 8,726,238
Evelyn Duesterwald, Robert M Fuhrer, Vijay Saraswat
US Patent 8,726,238
Exploring the impact of changing project parameters on the likely delivery date of a project
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/179,140
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 14/179,140
2013
Predicting likelihood of on-time product delivery, diagnosing issues that threaten delivery, and exploration of likely outcome of different solutions
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Dharmashankar Subramanian, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 13/906,490
Murray R Cantor, Evelyn Duesterwald, Tamir Klinger, Peter K Malkin, Paul M Matchen, Dharmashankar Subramanian, Stanley M Sutton, Peri L Tarr, Mark N Wegman
US Patent App. 13/906,490
Continuous updating of technical debt status
Evelyn Duesterwald, Tamir Klinger
US Patent App. 13/785,009
Evelyn Duesterwald, Tamir Klinger
US Patent App. 13/785,009
2009
Method for vertical integrated performance and environment monitoring
G C Cascaval, E Duesterwald, P F Sweeney, R W Wisniewski
US Patent 7,610,266
G C Cascaval, E Duesterwald, P F Sweeney, R W Wisniewski
US Patent 7,610,266
METHOD TO COMPUTE WAIT TIME
E. Duesterwald, P.K. Malkin, P.F. Sweeney, Q. Teng, H. Wang, X. Zhong
US Patent App. 12/562,659
E. Duesterwald, P.K. Malkin, P.F. Sweeney, Q. Teng, H. Wang, X. Zhong
US Patent App. 12/562,659
2008
MECHANISM FOR ADAPTIVE PROFILING FOR PERFORMANCE ANALYSIS
Y Chen, E Duesterwald, Y Li, Q M Teng
US Patent App. 12/130,718
Y Chen, E Duesterwald, Y Li, Q M Teng
US Patent App. 12/130,718
2007
METHOD AND SYSTEM FOR DETECTING SYNCHRONIZATION ERRORS IN PROGRAMS
E Duesterwald, Y Zhang
US Patent App. 20,080/201,629
E Duesterwald, Y Zhang
US Patent App. 20,080/201,629
METHOD AND SYSTEM FOR OPTIMIZING COMMUNICATION IN MPI PROGRAMS FOR AN EXECUTION ENVIRONMENT
G Cascaval, E Duesterwald, S E Smith, P F Sweeney, R W Wisniewski
US Patent App. 20,080/288,957
G Cascaval, E Duesterwald, S E Smith, P F Sweeney, R W Wisniewski
US Patent App. 20,080/288,957
MECHANISM FOR ON-LINE PREDICTION OF FUTURE PERFORMANCE MEASUREMENTS IN A COMPUTER SYSTEM
G C Cascaval, E Duesterwald, S Dwarkadas
US Patent App. 20,080/059,968
G C Cascaval, E Duesterwald, S Dwarkadas
US Patent App. 20,080/059,968
2006
Method for improving performance of executable code
G Cascaval, S Chatterjee, E Duesterwald, A Kielstra, K Stoodley
US Patent App. 20,070/226,698
G Cascaval, S Chatterjee, E Duesterwald, A Kielstra, K Stoodley
US Patent App. 20,070/226,698
Method and system for predicting the performance benefits of mapping subsets of application data to multiple page sizes
G C Cascaval, E Duesterwald, P F Sweeney, R W Wisniewski
US Patent App. 20,070/180,215
G C Cascaval, E Duesterwald, P F Sweeney, R W Wisniewski
US Patent App. 20,070/180,215
2005
Dynamic execution layer interface for replacing instructions requiring unavailable hardware functionality with patch code and caching
E Duesterwald, S M Freudenberger
US Patent 6,928,536
E Duesterwald, S M Freudenberger
US Patent 6,928,536
System and method for vertical integrated performance and environment monitoring
G C Cascaval, E Duesterwald, P F Sweeney, R W Wisniewski
US Patent App. 20,060/271,827
G C Cascaval, E Duesterwald, P F Sweeney, R W Wisniewski
US Patent App. 20,060/271,827
2004
Method and system for fast unlinking of a linked branch in a caching dynamic translator
Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia
US Patent 6,725,335
Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia
US Patent 6,725,335
2003
2002
Systems and methods for verifying correct execution of emulated code via dynamic state verification
G Desoli, V Bala, E Duesterwald
US Patent App. 20,030/182,653
G Desoli, V Bala, E Duesterwald
US Patent App. 20,030/182,653
2001
Speculative caching scheme for fast emulation through statically predicted execution traces in a caching dynamic translator
E Duesterwald, V Bala, S Banerjia
US Patent App. 09/756,019
E Duesterwald, V Bala, S Banerjia
US Patent App. 09/756,019
Partitioned code cache organization to exploit program locallity
S Banerjia, E Duesterwald, V Bala
US Patent App. 20,010/049,818
S Banerjia, E Duesterwald, V Bala
US Patent App. 20,010/049,818
Fast runtime scheme for removing dead code across linked fragments
E Duesterwald, V Bala, S Banerjia
US Patent App. 20,020/013,938
E Duesterwald, V Bala, S Banerjia
US Patent App. 20,020/013,938
System and method for supporting emulation of a computer system through dynamic code caching and transformation
G Desoli, V Bala, E Duesterwald
US Patent App. 09/997,163
G Desoli, V Bala, E Duesterwald
US Patent App. 09/997,163
System and method for dynamically patching code
E Duesterwald, S M Freudenberger
US Patent App. 09/995,775
E Duesterwald, S M Freudenberger
US Patent App. 09/995,775
Secondary trace build from a cache of translations in a caching dynamic translator
E Duesterwald, V Bala, S Banerjia
US Patent App. 20,010/042,172
E Duesterwald, V Bala, S Banerjia
US Patent App. 20,010/042,172
Memory disambiguation scheme for partially redundant load removal
E Duesterwald, V Bala, S Banerjia
US Patent App. 20,010/032,306
E Duesterwald, V Bala, S Banerjia
US Patent App. 20,010/032,306
Method and apparatus for profiling of non-instrumented programs and dynamic processing of profile data
V Bala
US Patent 6,233,678
V Bala
US Patent 6,233,678
Annotations to executable images for improved dynamic optimization of functions
S M Freudenberger, E Duesterwald
US Patent App. 20,030/093,780
S M Freudenberger, E Duesterwald
US Patent App. 20,030/093,780
System and method for dynamically replacing code
E Duesterwald, S M Freudenberger
US Patent App. 20,030/101,431
E Duesterwald, S M Freudenberger
US Patent App. 20,030/101,431
Preemptive replacement strategy for a caching dynamic translator
S Banerjia, V Bala, E Duesterwald
US Patent 6,237,065
S Banerjia, V Bala, E Duesterwald
US Patent 6,237,065
Dynamic execution layer interface for explicitly or transparently executing application or system binaries
E Duesterwald, G Desoli, P Faraboschi, J A Fisher, V Bala
US Patent App. 20,030/033,593
E Duesterwald, G Desoli, P Faraboschi, J A Fisher, V Bala
US Patent App. 20,030/033,593
Portable run-time code synthesis in a caching dynamic translator
E Duesterwald, G Desoli, V Bala
US Patent App. 20,030/110,478
E Duesterwald, G Desoli, V Bala
US Patent App. 20,030/110,478
1999
Low overhead speculative selection of hot traces in a caching dynamic translator
V Bala, E Duesterwald
US Patent App. 20,020/104,075
V Bala, E Duesterwald
US Patent App. 20,020/104,075