# Eric M Schwarz
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## contact information

Distinguished Engineer, z Systems and Power Core Logic Design and Arithmetic Hardware Expert

Poughkeepsie, NY

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Poughkeepsie, NY

## links

### Professional Associations

**Professional Associations:**IEEE | IEEE Computer Society | IEEE Mid-Hudson Section | IEEE, Senior Member

### more information

**More information:**Symposium on Computer Arithmetic - Steering Committee - General Chair

**2018**

Non-default instruction handling within transaction

Bradbury, Jonathan D and Gschwind, Michael K and Michael, Maged M and Schwarz, Eric M and Salapura, Valentina and Shum, Chung-Lung K

US Patent 9,858,074

Abstract

Bradbury, Jonathan D and Gschwind, Michael K and Michael, Maged M and Schwarz, Eric M and Salapura, Valentina and Shum, Chung-Lung K

US Patent 9,858,074

Abstract

Hardware transaction transient conflict resolution

Bradbury, Jonathan D and Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-Lung K and Slegel, Timothy J

US Patent 9,952,804

Abstract

Bradbury, Jonathan D and Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-Lung K and Slegel, Timothy J

US Patent 9,952,804

Abstract

DECIMAL SHIFT AND DIVIDE INSTRUCTION

Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia Melitta Mueller, Eric M. Schwarz

decimal, arithmetic, computer science

Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia Melitta Mueller, Eric M. Schwarz

decimal, arithmetic, computer science

CONTROL STATE PRESERVATION DURING TRANSACTIONAL EXECUTION

Jonathan D. Bradbury, Michael Karl Gschwind, Eric M. Schwarz, Chung-lung K. Shum

transactional leadership, database, computer science

Jonathan D. Bradbury, Michael Karl Gschwind, Eric M. Schwarz, Chung-lung K. Shum

transactional leadership, database, computer science

**2017**

Collecting transactional execution characteristics during transactional execution

Busaba, Fadi Y and Cain III, Harold W and Greiner, Dan F and Gschwind, Michael Karl and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-Lung K

US Patent 9,710,271

Abstract

Busaba, Fadi Y and Cain III, Harold W and Greiner, Dan F and Gschwind, Michael Karl and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-Lung K

US Patent 9,710,271

Abstract

Address probing for transaction

Busaba, Fadi Y and Cain III, Harold W and Greiner, Dan F and Gschwind, Michael K and Michael, Maged M and Schwarz, Eric M and Salapura, Valentina and Slegel, Timothy J

US Patent 9,766,829

Abstract

Busaba, Fadi Y and Cain III, Harold W and Greiner, Dan F and Gschwind, Michael K and Michael, Maged M and Schwarz, Eric M and Salapura, Valentina and Slegel, Timothy J

US Patent 9,766,829

Abstract

Instruction to cancel outstanding cache prefetches

Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-Lung K

US Patent 9,535,696

Abstract

Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-Lung K

US Patent 9,535,696

Abstract

STOCHASTIC ROUNDING FLOATING-POINT MULTIPLY INSTRUCTION USING ENTROPY FROM A REGISTER

Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz

bit slicing, operand, rounding, least significant bit, central processing unit, floating point, computer hardware, parallel computing, computer science

Abstract

Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz

bit slicing, operand, rounding, least significant bit, central processing unit, floating point, computer hardware, parallel computing, computer science

Abstract

Floating point instruction with selectable comparison attributes

Jonathan D. Bradbury, Michael K. Gschwind, Silvia Melitta Mueller, Brett Olsson, Eric M. Schwarz

floating point, arithmetic, computer hardware, computer science

Jonathan D. Bradbury, Michael K. Gschwind, Silvia Melitta Mueller, Brett Olsson, Eric M. Schwarz

floating point, arithmetic, computer hardware, computer science

Prioritization of transactions based on execution by transactional core with super core indicator

Busaba, Fadi Y and Cain III, Harold W and Gschwind, Michael K and Salapura, Valentina and Schwarz, Eric M and Slegel, Timothy J

US Patent 9,772,874

Abstract

Busaba, Fadi Y and Cain III, Harold W and Gschwind, Michael K and Salapura, Valentina and Schwarz, Eric M and Slegel, Timothy J

US Patent 9,772,874

Abstract

TRANSACTIONAL MEMORY COHERENCE CONTROL

Fadi Y. Busaba, Harold W. Cain Iii, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

cache only memory architecture, transactional memory, behavioral pattern, coherence, computer program, real time computing, computer science

Abstract

Fadi Y. Busaba, Harold W. Cain Iii, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

cache only memory architecture, transactional memory, behavioral pattern, coherence, computer program, real time computing, computer science

Abstract

REGULATING HARDWARE SPECULATIVE PROCESSING AROUND A TRANSACTION

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum

database transaction, computer hardware, business

Abstract

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum

database transaction, computer hardware, business

Abstract

Transactional memory system including cache versioning architecture to implement nested transactions

Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-lung K. Shum

cache only memory architecture, nested transaction, software transactional memory, cache coloring, transactional memory, cache, thread, database transaction, real time computing, parallel computing, computer science

Abstract

Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-lung K. Shum

cache only memory architecture, nested transaction, software transactional memory, cache coloring, transactional memory, cache, thread, database transaction, real time computing, parallel computing, computer science

Abstract

Interprocessor memory status communication

Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-lung K and Slegel, Timothy J

US Patent 9,563,467

Abstract

Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Shum, Chung-lung K and Slegel, Timothy J

US Patent 9,563,467

Abstract

Suspending branch prediction upon entering transactional execution mode

Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-lung Shum

transactional leadership, branch predictor, real time computing, computer science

Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-lung Shum

transactional leadership, branch predictor, real time computing, computer science

PRIORITIZATION OF TRANSACTIONS

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

transactional leadership, prioritization, database transaction, computer program, real time computing, computer science

Abstract

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

transactional leadership, prioritization, database transaction, computer program, real time computing, computer science

Abstract

Mechanism for creating friendly transactions with credentials

Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum

x open xa, compensating transaction, nested transaction, transaction processing system, distributed transaction, transaction data, transaction processing, database transaction, real time computing, database, business

Abstract

Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum

x open xa, compensating transaction, nested transaction, transaction processing system, distributed transaction, transaction data, transaction processing, database transaction, real time computing, database, business

Abstract

PARTIAL STOCHASTIC ROUNDING THAT INCLUDES STICKY AND GUARD BITS

Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz

rounding, guard, theoretical computer science, computer science

Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz

rounding, guard, theoretical computer science, computer science

**2016**

Multi-Granular Cache Management in Multi-Processor Computing Environments

F Busaba, H Cain, M Gschwind, M Michael, V Salapura, E Schwarz, CL Shum

US Patent 9,292,444

F Busaba, H Cain, M Gschwind, M Michael, V Salapura, E Schwarz, CL Shum

US Patent 9,292,444

Transactional processing based upon run-time conditions

MK Gschwind, MM Michael, V Salapura, EM Schwarz, CLK Shum

US Patent 9,262,343

MK Gschwind, MM Michael, V Salapura, EM Schwarz, CLK Shum

US Patent 9,262,343

Prefetching of discontiguous storage locations in anticipation of transactional execution

Busaba, Fadi Y and Greiner, Dan F and Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Slegel, Timothy J

US Patent 9,336,047

Abstract

Busaba, Fadi Y and Greiner, Dan F and Gschwind, Michael Karl and Michael, Maged M and Salapura, Valentina and Schwarz, Eric M and Slegel, Timothy J

US Patent 9,336,047

Abstract

Salvaging hardware transactions with instructions

FY Busaba, HW Cain, MM Michael, V Salapura, EM Schwarz

US Patent 9,311,178

FY Busaba, HW Cain, MM Michael, V Salapura, EM Schwarz

US Patent 9,311,178

Salvaging hardware transactions

HW Cain III, MK Gschwind, MM Michael, V Salapura, EM Schwarz

US Patent 9,244,782

HW Cain III, MK Gschwind, MM Michael, V Salapura, EM Schwarz

US Patent 9,244,782

REGISTER COMPARISON FOR OPERAND STORE COMPARE (OSC) PREDICTION

David Hutton, Wen Li, Eric Schwarz

index register, indirect branch, addressing mode, program counter, instruction register, status register, memory data register, operand, computer architecture, computer science

Abstract

David Hutton, Wen Li, Eric Schwarz

index register, indirect branch, addressing mode, program counter, instruction register, status register, memory data register, operand, computer architecture, computer science

Abstract

Convert to zoned format from decimal floating point format

Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel

decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, ebcdic, double precision floating point format, floating point, computer hardware, parallel

Abstract

Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel

decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, ebcdic, double precision floating point format, floating point, computer hardware, parallel

Abstract

**2015**

Centralized management of high-contention cache lines in multi-processor computing environments

FY Busaba, HW Cain III, MK Gschwind, MM Michael, V Salapura, EM Schwarz, CLK Shum

US Patent 9,086,974

FY Busaba, HW Cain III, MK Gschwind, MM Michael, V Salapura, EM Schwarz, CLK Shum

US Patent 9,086,974

Recovering hardware transactions

Maged Milad Michael, Michael K. Gschwind, Harold Wade Cain, Valentina Salapura, Eric Mark Schwarz

extreme transaction processing, x open xa, hardware compatibility list, transaction processing system, online transaction processing, distributed transaction, transaction data, transaction processing, computer hardware, real time computing, computer scien

Abstract

Maged Milad Michael, Michael K. Gschwind, Harold Wade Cain, Valentina Salapura, Eric Mark Schwarz

extreme transaction processing, x open xa, hardware compatibility list, transaction processing system, online transaction processing, distributed transaction, transaction data, transaction processing, computer hardware, real time computing, computer scien

Abstract

Transaction tracking within a microprocessor

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz

extreme transaction processing, x open xa, compensating transaction, nested transaction, transaction processing system, distributed transaction, transaction data, transaction processing, real time computing, business

Abstract

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz

extreme transaction processing, x open xa, compensating transaction, nested transaction, transaction processing system, distributed transaction, transaction data, transaction processing, real time computing, business

Abstract

Instruction stream tracing of multi-threaded processors

Lee E. Eisen, Lisa C. Heller, Michael T. Huffer, Eric M. Schwarz

win32 thread information block, tracing, thread, streams, computer hardware, parallel computing, computer science

Abstract

Lee E. Eisen, Lisa C. Heller, Michael T. Huffer, Eric M. Schwarz

win32 thread information block, tracing, thread, streams, computer hardware, parallel computing, computer science

Abstract

DETECTING CACHE CONFLICTS BY UTILIZING LOGICAL ADDRESS COMPARISONS IN A TRANSACTIONAL MEMORY

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

uniform memory access, memory map, logical address, memory address, flat memory model, physical address, address space, virtual memory, computer architecture, computer science

Abstract

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

uniform memory access, memory map, logical address, memory address, flat memory model, physical address, address space, virtual memory, computer architecture, computer science

Abstract

ALLOCATING READ BLOCKS TO A THREAD IN A TRANSACTION USING USER SPECIFIED LOGICAL ADDRESSES

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

page address register, kernel virtual address space, logical address, virtual address space, physical address, address bus, address space, thread, real time computing, parallel computing, computer science

Abstract

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

page address register, kernel virtual address space, logical address, virtual address space, physical address, address bus, address space, thread, real time computing, parallel computing, computer science

Abstract

Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor

Jonathan D. Bradbury, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

pipeline burst cache, non uniform memory access, uniform memory access, application specific instruction set processor, processor affinity, processor register, address bus, memory buffer register, parallel computing, computer science

Abstract

Jonathan D. Bradbury, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

pipeline burst cache, non uniform memory access, uniform memory access, application specific instruction set processor, processor affinity, processor register, address bus, memory buffer register, parallel computing, computer science

Abstract

Conditional inclusion of data in a transactional memory read set

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

pipeline burst cache, mesif protocol, mesi protocol, write once, cache pollution, cache coloring, cache algorithms, cache, parallel computing, computer science

Abstract

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

pipeline burst cache, mesif protocol, mesi protocol, write once, cache pollution, cache coloring, cache algorithms, cache, parallel computing, computer science

Abstract

TRANSACTIONAL EXECUTION IN A MULTI-PROCESSOR ENVIRONMENT THAT MONITORS MEMORY CONFLICTS IN A SHARED CACHE

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum

bus sniffing, snoopy cache, smart cache, cache pollution, cache invalidation, cache coloring, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum

bus sniffing, snoopy cache, smart cache, cache pollution, cache invalidation, cache coloring, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Managing read tags in a transactional memory

Dan F. Greiner, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

snoopy cache, page cache, smart cache, cache pollution, cache invalidation, cache coloring, cache algorithms, cache, parallel computing, computer science

Abstract

Dan F. Greiner, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

snoopy cache, page cache, smart cache, cache pollution, cache invalidation, cache coloring, cache algorithms, cache, parallel computing, computer science

Abstract

SYSTEM OPERATION QUEUE FOR TRANSACTION

Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz

transaction processing system, transaction data, transaction processing, database transaction, central processing unit, queue, real time computing, business

Abstract

Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz

transaction processing system, transaction data, transaction processing, database transaction, central processing unit, queue, real time computing, business

Abstract

Co-processor memory accesses in a transactional memory

Jonathan D. Bradbury, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

pipeline burst cache, extended memory, non uniform memory access, uniform memory access, transactional memory, processor register, memory buffer register, semiconductor memory, real time computing, parallel computing, computer science

Abstract

Jonathan D. Bradbury, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

pipeline burst cache, extended memory, non uniform memory access, uniform memory access, transactional memory, processor register, memory buffer register, semiconductor memory, real time computing, parallel computing, computer science

Abstract

Dynamic predictor for coalescing memory transactions

Fadi Y. Busaba, Harold W. Cain, Michael Karl Gschwind, Maged M. Michael, Eric M. Schwarz

compensating transaction, distributed transaction, transactional memory, abort, database transaction, real time computing, parallel computing, computer science

Abstract

Fadi Y. Busaba, Harold W. Cain, Michael Karl Gschwind, Maged M. Michael, Eric M. Schwarz

compensating transaction, distributed transaction, transactional memory, abort, database transaction, real time computing, parallel computing, computer science

Abstract

Coherence protocol augmentation to indicate transaction status

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Christian Jacobi, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

transaction processing system, database transaction, coherence, real time computing, computer science

Abstract

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Christian Jacobi, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

transaction processing system, database transaction, coherence, real time computing, computer science

Abstract

EVADING FLOATING INTERRUPTION WHILE IN THE TRANSACTIONAL-EXECUTION MODE

Jonathan D. Bradbury, Fadi Y. Busaba, Harold W. Cain Iii, Dan F. Greiner, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz

interrupt, transactional leadership, real time computing, computer science

Abstract

Jonathan D. Bradbury, Fadi Y. Busaba, Harold W. Cain Iii, Dan F. Greiner, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz

interrupt, transactional leadership, real time computing, computer science

Abstract

Transactional execution processor having a co-processor accelerator, both sharing a higher level cache

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-lung K. Shum

pipeline burst cache, snoopy cache, smart cache, cache pollution, cache invalidation, cache coloring, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-lung K. Shum

pipeline burst cache, snoopy cache, smart cache, cache pollution, cache invalidation, cache coloring, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Transactional memory operations with read-only atomicity

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

commitment ordering, software transactional memory, distributed transaction, atomicity, transactional memory, transactional leadership, database transaction, central processing unit, real time computing, parallel computing, computer science

Abstract

Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

commitment ordering, software transactional memory, distributed transaction, atomicity, transactional memory, transactional leadership, database transaction, central processing unit, real time computing, parallel computing, computer science

Abstract

**2014**

Vectorized Galois field multiplication

James R. Cuffney, John G. Rell, Eric M. Schwarz, Patrick M. West

operand, galois theory, multiplication, parity, discrete mathematics, algebra, mathematics

Abstract

James R. Cuffney, John G. Rell, Eric M. Schwarz, Patrick M. West

operand, galois theory, multiplication, parity, discrete mathematics, algebra, mathematics

Abstract

Optimizing grouping of instructions

Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Eric M. Schwarz, Aaron Tsai

microprocessor, queue, computer hardware, real time computing, computer science

Abstract

Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Eric M. Schwarz, Aaron Tsai

microprocessor, queue, computer hardware, real time computing, computer science

Abstract

Prefetching of discontiguous storage locations as part of transactional execution

Fadi Y. Busaba, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

transactional leadership, indirection, cache, database transaction, metadata, parallel computing, database, computer science

Abstract

Fadi Y. Busaba, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel

transactional leadership, indirection, cache, database transaction, metadata, parallel computing, database, computer science

Abstract

Suspending Branch Prediction in Transactional Memory Instruction Execution

Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung Shum

branch, indirect branch, transactional memory, pipeline, branch predictor, database transaction, real time computing, parallel computing, computer science

Abstract

Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung Shum

branch, indirect branch, transactional memory, pipeline, branch predictor, database transaction, real time computing, parallel computing, computer science

Abstract

Vector floating point test data class immediate instruction

Jonathan David Bradbury, Eric Mark Schwarz

operand, test data, floating point, discrete mathematics, real time computing, mathematics

Abstract

Jonathan David Bradbury, Eric Mark Schwarz

operand, test data, floating point, discrete mathematics, real time computing, mathematics

Abstract

SPECULATION CONTROL FOR IMPROVING TRANSACTION SUCCESS RATE, AND INSTRUCTION THEREFOR

Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

transaction processing system, operand, bandwidth throttling, instructions per cycle, speculation, database transaction, computer hardware, real time computing, computer science

Abstract

Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel

transaction processing system, operand, bandwidth throttling, instructions per cycle, speculation, database transaction, computer hardware, real time computing, computer science

Abstract

Convert from zoned format to decimal floating point format

Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel

decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, ebcdic, double precision floating point format, floating point, computer hardware, parallel

Abstract

Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel

decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, ebcdic, double precision floating point format, floating point, computer hardware, parallel

Abstract

Vector generate mask instruction

Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel

addressing mode, mask, operand, computer hardware, parallel computing, computer science

Abstract

Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel

addressing mode, mask, operand, computer hardware, parallel computing, computer science

Abstract

Indicating a low priority transaction

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz

x open xa, priority inheritance, priority ceiling protocol, priority call, distributed transaction, transaction processing, transactional leadership, database transaction, distributed computing, real time computing, business

Abstract

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz

x open xa, priority inheritance, priority ceiling protocol, priority call, distributed transaction, transaction processing, transactional leadership, database transaction, distributed computing, real time computing, business

Abstract

Supporting atomic accumulation with an addressable accumulator

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz

accumulator, identifier, queue, computer hardware, real time computing, computer science

Abstract

Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz

accumulator, identifier, queue, computer hardware, real time computing, computer science

Abstract

**2013**

Anweisung "Vector generate mask" Instructions "Vector generate mask"

Jonathan David Bradbury, Timothy Slegel, Eric Mark Schwarz, Robert Frederick Enenkel

mask, operand, computer hardware, computer science

Abstract

Jonathan David Bradbury, Timothy Slegel, Eric Mark Schwarz, Robert Frederick Enenkel

mask, operand, computer hardware, computer science

Abstract

Instruction vecteur trouver element egal

Jonathan David Bradbury, Timothy Slegel, Eric Mark Schwarz, Michael Karl Gschwind

Jonathan David Bradbury, Timothy Slegel, Eric Mark Schwarz, Michael Karl Gschwind

Method of loading data up to a dynamically determined memory boundary

Jonathan David Bradbury, Michael Karl Gschwind, Timothy Slegel, Eric Mark Schwarz, Christian Jacobi

cpu cache, byte, page, parallel computing, computer science

Abstract

Jonathan David Bradbury, Michael Karl Gschwind, Timothy Slegel, Eric Mark Schwarz, Christian Jacobi

cpu cache, byte, page, parallel computing, computer science

Abstract

Find regular expression instruction on substring of larger string

Eric M. Schwarz

longest repeated substring problem, substring index, substring, byte, string, regular expression, pattern matching, theoretical computer science, computer science

Abstract

Eric M. Schwarz

longest repeated substring problem, substring index, substring, byte, string, regular expression, pattern matching, theoretical computer science, computer science

Abstract

Vector element rotate and insert under mask instruction

Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel

operand, rotation, computer hardware, parallel computing, computer science

Abstract

Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel

operand, rotation, computer hardware, parallel computing, computer science

Abstract

MANAGING HIGH-COHERENCE-MISS CACHE LINES IN MULTI-PROCESSOR COMPUTING ENVIRONMENTS

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum

mesif protocol, mesi protocol, snoopy cache, smart cache, cache pollution, cache invalidation, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum

mesif protocol, mesi protocol, snoopy cache, smart cache, cache pollution, cache invalidation, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Vector checksum instruction

Jonathan David Bradbury, Eric Mark Schwarz

checksum, operand, computer hardware, parallel computing, computer science

Abstract

Jonathan David Bradbury, Eric Mark Schwarz

checksum, operand, computer hardware, parallel computing, computer science

Abstract

Run-time instrumentation indirect sampling by instruction operation code

Jonathan David Bradbury, Charles W. Gainey Jr., Michael Karl Gschwind, Eric Mark Schwarz

instruction path length, orthogonal instruction set, self modifying code, minimal instruction set computer, addressing mode, instruction register, instrumentation, instruction cycle, computer hardware, computer science

Abstract

Jonathan David Bradbury, Charles W. Gainey Jr., Michael Karl Gschwind, Eric Mark Schwarz

instruction path length, orthogonal instruction set, self modifying code, minimal instruction set computer, addressing mode, instruction register, instrumentation, instruction cycle, computer hardware, computer science

Abstract

Modify and Execute Next Sequential Instruction Facility and Instructions Therefore

Michael K. Gschwind, Eric M. Schwarz

instruction register, instruction set, prefix, real time computing, computer science

Abstract

Michael K. Gschwind, Eric M. Schwarz

instruction register, instruction set, prefix, real time computing, computer science

Abstract

Instruction to load data up to a dynamically determined memory boundary

Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel

cpu cache, byte, page, parallel computing, computer science

Abstract

Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel

cpu cache, byte, page, parallel computing, computer science

Abstract

Vector find element not equal instruction

Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel

inequality, discrete mathematics, arithmetic, mathematics

Abstract

Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel

inequality, discrete mathematics, arithmetic, mathematics

Abstract

Round for reround mode in a decimal floating point instruction

Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal floating point, significant figures, leading zero, numerical digit, decimal, rounding, least significant bit, floating point, arithmetic, computer hardware, mathematics

Abstract

Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal floating point, significant figures, leading zero, numerical digit, decimal, rounding, least significant bit, floating point, arithmetic, computer hardware, mathematics

Abstract

Vector exception code

Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel

exception handling, simulation, real time computing, computer science

Abstract

Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel

exception handling, simulation, real time computing, computer science

Abstract

Identifying high-conflict cache lines in transactional memory computing environments

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum

mesif protocol, mesi protocol, snoopy cache, write once, cache pollution, cache coloring, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Fadi Y. Busaba, Harold W. Cain, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum

mesif protocol, mesi protocol, snoopy cache, write once, cache pollution, cache coloring, cache algorithms, cache, real time computing, parallel computing, computer science

Abstract

Vector string range compare

Jonathan David Bradbury, Eric Mark Schwarz, Timothy Slegel

string, theoretical computer science, mathematics

Abstract

Jonathan David Bradbury, Eric Mark Schwarz, Timothy Slegel

string, theoretical computer science, mathematics

Abstract

**2012**

Instruction to load data up to a specified memory boundary indicated by the instruction

Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel

indirect branch, instruction register, instruction cycle, byte, opcode, computer architecture, parallel computing, computer science

Abstract

Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel

indirect branch, instruction register, instruction cycle, byte, opcode, computer architecture, parallel computing, computer science

Abstract

**2011**

Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor

David S Hutton, Khary J Alexander, Fadi Y Busaba, Bruce C Giamei, John G Rell Jr, Eric M Schwarz, Chung-Lung Kevin Shum

US Patent 7,913,067

David S Hutton, Khary J Alexander, Fadi Y Busaba, Bruce C Giamei, John G Rell Jr, Eric M Schwarz, Chung-Lung Kevin Shum

US Patent 7,913,067

Triggering workaround capabilities based on events active in a processor pipeline

Gregory W Alexander, Fadi Busaba, David A Schroter, Eric Schwarz, Brian W Thompto, Wesley J Ward III

US Patent 8,082,467

Gregory W Alexander, Fadi Busaba, David A Schroter, Eric Schwarz, Brian W Thompto, Wesley J Ward III

US Patent 8,082,467

***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***Shift significand of decimal floating point data

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith Sr., Phil C. Yeh

decimal floating point, significand, arithmetic, computer hardware, computer science

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith Sr., Phil C. Yeh

decimal floating point, significand, arithmetic, computer hardware, computer science

Emulating hexadecimal floating-point operations in non-native systems

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, floating point, binary number, latency, architecture, parallel computing, computer science

Abstract

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, floating point, binary number, latency, architecture, parallel computing, computer science

Abstract

**2010**

System and method for performing decimal to binary conversion

Steven R Carlough, Bruce M Fleischer, Wen H Li, Eric M Schwarz

US Patent 7,660,838

Steven R Carlough, Bruce M Fleischer, Wen H Li, Eric M Schwarz

US Patent 7,660,838

System and method for a floating point unit with feedback prior to normalization and rounding

Bruce M Fleischer, Juergen Haess, Michael Kroener, Martin S Schmookler, Eric M Schwarz, Son Dao-Trong

US Patent 7,730,117

Bruce M Fleischer, Juergen Haess, Michael Kroener, Martin S Schmookler, Eric M Schwarz, Son Dao-Trong

US Patent 7,730,117

Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator

Daniel Lipetz, Bruce M Fleischer, Eric M Schwarz

US Patent 7,739,323

Daniel Lipetz, Bruce M Fleischer, Eric M Schwarz

US Patent 7,739,323

Dezimal-schwebepunkt-quantumausnahmeerkennung

Eric Mark Schwarz, Phil Yeh, Michael Frederic Cowlishaw, Silvia Melitta Mueller

Eric Mark Schwarz, Phil Yeh, Michael Frederic Cowlishaw, Silvia Melitta Mueller

Instruction cracking based on machine state

Fadi Busaba, Bruce Giamei, David Hutton, Eric Schwarz

US Patent App. 12/718,685

Fadi Busaba, Bruce Giamei, David Hutton, Eric Schwarz

US Patent App. 12/718,685

Decimal Floating-Point Quantum Exception Detection

Michael F. Cowlishaw, Silvia Melitta Mueller, Eric Schwarz, Phil C. Yeh

decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, double precision floating point format, fixed point arithmetic, significant figures, leading zero, arithmetic, computer hardware, m

Abstract

Michael F. Cowlishaw, Silvia Melitta Mueller, Eric Schwarz, Phil C. Yeh

decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, double precision floating point format, fixed point arithmetic, significant figures, leading zero, arithmetic, computer hardware, m

Abstract

**2009**

Method and apparatus for prefetching branch history information

Philip G Emma, Klaus J Getzlaff, Allan M Hartstein, Thomas Pflueger, Thomas R Puzak, Eric Mark Schwarz, Vijayalakshmi Srinivasan

US Patent 7,493,480

Philip G Emma, Klaus J Getzlaff, Allan M Hartstein, Thomas Pflueger, Thomas R Puzak, Eric Mark Schwarz, Vijayalakshmi Srinivasan

US Patent 7,493,480

Method for Performing Decimal Floating Point Addition

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

decimal floating point, operand, subtraction, arithmetic, parallel computing, mathematics

Abstract

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

decimal floating point, operand, subtraction, arithmetic, parallel computing, mathematics

Abstract

Multifunction hexadecimal instruction form system and program product

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, binary number, latency, architecture, parallel computing, computer science

Abstract

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, binary number, latency, architecture, parallel computing, computer science

Abstract

Method for Providing a Decimal Multiply Algorithm Using a Double Adder

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

running total, significant figures, multiple, operand, numerical digit, decimal, least significant bit, adder, arithmetic, computer hardware, algorithm, mathematics

Abstract

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

running total, significant figures, multiple, operand, numerical digit, decimal, least significant bit, adder, arithmetic, computer hardware, algorithm, mathematics

Abstract

System and Method for Providing a Double Adder for Decimal Floating Point Operations

Steven R. Carlough, Wilhelm E. Haller, Wen H. Li, Eric M. Schwarz

decimal floating point, carry save adder, operand, adder, arithmetic, parallel computing, mathematics

Abstract

Steven R. Carlough, Wilhelm E. Haller, Wen H. Li, Eric M. Schwarz

decimal floating point, carry save adder, operand, adder, arithmetic, parallel computing, mathematics

Abstract

Method for Performing Decimal Division

Steven R. Carlough, Paulomi Kadakia, Wen H. Li, Eric M. Schwarz

multiple, remainder, numerical digit, decimal, divisor, quotient, dividend, discrete mathematics, arithmetic, mathematics

Abstract

Steven R. Carlough, Paulomi Kadakia, Wen H. Li, Eric M. Schwarz

multiple, remainder, numerical digit, decimal, divisor, quotient, dividend, discrete mathematics, arithmetic, mathematics

Abstract

Dual issuing of complex instruction set instructions

Fadi Busaba, Brian Curran, Lee Eisen, Christian Jacobi, David A Schroter, Eric Schwarz

US Patent App. 12/645,716

Fadi Busaba, Brian Curran, Lee Eisen, Christian Jacobi, David A Schroter, Eric Schwarz

US Patent App. 12/645,716

COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA

Gregory W. Alexander, Jane Bartik, Michael Billeci, David Hutton, Christian Jacobi, Jang-Soo Lee, Eric Schwarz, Chung-Lung Shum, Phil C. Yeh

sampling, pulse, central processing unit, architecture, instrumentation, computer hardware, real time computing, computer science

Abstract

Gregory W. Alexander, Jane Bartik, Michael Billeci, David Hutton, Christian Jacobi, Jang-Soo Lee, Eric Schwarz, Chung-Lung Shum, Phil C. Yeh

sampling, pulse, central processing unit, architecture, instrumentation, computer hardware, real time computing, computer science

Abstract

**2008**

Apparatus comprising a counter reduction tree for calculation of a residue of an operand

Guenter Gerwig, Bruce Martin Fleischer, Juergen Haess, Son Dao Trong, Eric Mark Schwarz, Holger Wetter

operand, residue, discrete mathematics, parallel computing, mathematics

Guenter Gerwig, Bruce Martin Fleischer, Juergen Haess, Son Dao Trong, Eric Mark Schwarz, Holger Wetter

operand, residue, discrete mathematics, parallel computing, mathematics

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR IDENTIFYING DECIMAL FLOATING POINT ADDITION OPERATIONS THAT DO NOT REQUIRE ALIGNMENT, NORMALIZATION OR ROUNDING

Adam B. Collura, Steven R. Carlough, Wen He Li, Eric M. Schwarz

decimal floating point, significant figures, operand, rounding, normalization, computer program, arithmetic, parallel computing, computer science

Abstract

Adam B. Collura, Steven R. Carlough, Wen He Li, Eric M. Schwarz

decimal floating point, significant figures, operand, rounding, normalization, computer program, arithmetic, parallel computing, computer science

Abstract

Identifying decimal floating point addition operations that do not require alignment, normalization or rounding

Adam B. Collura, Steven R. Carlough, Wen He Li, Eric M. Schwarz

decimal floating point, significant figures, operand, exponent, rounding, normalization, computer program, arithmetic, parallel computing, computer science

Abstract

Adam B. Collura, Steven R. Carlough, Wen He Li, Eric M. Schwarz

decimal floating point, significant figures, operand, exponent, rounding, normalization, computer program, arithmetic, parallel computing, computer science

Abstract

Execution of fixed point instructions using a decimal floating point unit

Steven R. Carlough, Adam B. Collura, Mark A. Erle, Wen H. Li, Eric M. Schwarz

decimal floating point, binary integer decimal, binary coded decimal, operand, fixed point, computer hardware, parallel computing, mathematics

Abstract

Steven R. Carlough, Adam B. Collura, Mark A. Erle, Wen H. Li, Eric M. Schwarz

decimal floating point, binary integer decimal, binary coded decimal, operand, fixed point, computer hardware, parallel computing, mathematics

Abstract

METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS

Steven R. Carlough, Adam B. Collura, Mark A. Erle, Wen H. Li, Eric M. Schwarz

decimal floating point, binary integer decimal, binary coded decimal, operand, fixed point, computer program, computer hardware, parallel computing, mathematics

Abstract

Steven R. Carlough, Adam B. Collura, Mark A. Erle, Wen H. Li, Eric M. Schwarz

decimal floating point, binary integer decimal, binary coded decimal, operand, fixed point, computer program, computer hardware, parallel computing, mathematics

Abstract

Method And Decimal Arithmetic Logic Unit Structure To Generate A Magnitude Result of a Mathematic

Wilhelm Haller, Ulrich Krauch, Guenter Mayer, Eric M. Schwarz

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, decimal, arithmetic, mathematics

Abstract

Wilhelm Haller, Ulrich Krauch, Guenter Mayer, Eric M. Schwarz

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, decimal, arithmetic, mathematics

Abstract

Processor and method for workaround trigger activated exceptions

Steven R. Carlough, Adam B. Collura, Wen H. Li, Eric M. Schwarz, Chung-Lung Kevin Shum

microarchitecture, workaround, detector, real time computing, computer science

Abstract

Steven R. Carlough, Adam B. Collura, Wen H. Li, Eric M. Schwarz, Chung-Lung Kevin Shum

microarchitecture, workaround, detector, real time computing, computer science

Abstract

**2007**

System and method for creating precise exceptions

Fadi Y Busaba, Michael J Mack, John G Rell Jr, Eric M Schwarz, Chung-Lung K Shum, Timothy J Slegel, Scott B Swaney, Sheryll H Veneracion

US Patent 7,200,742

Fadi Y Busaba, Michael J Mack, John G Rell Jr, Eric M Schwarz, Chung-Lung K Shum, Timothy J Slegel, Scott B Swaney, Sheryll H Veneracion

US Patent 7,200,742

Employing a mask field of an instruction to encode a sign of a result of the instruction

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

Insert/extract biased exponent of decimal floating point data

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, computer sci

Abstract

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, computer sci

Abstract

COMPOSITION/DECOMPOSITION OF DECIMAL FLOATING POINT DATA

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, mathematics

Abstract

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, mathematics

Abstract

COMPOSITION OF DECIMAL FLOATING POINT DATA, AND METHODS THEREFOR

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

EXTRACT BIASED EXPONENT OF DECIMAL FLOATING POINT DATA

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, mathematics

Abstract

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, mathematics

Abstract

DECOMPOSITION OF DECIMAL FLOATING POINT DATA

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, mathematics

Abstract

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, decimal representation, binary integer decimal, double precision floating point format, arithmetic, mathematics

Abstract

Shift significand of decimal floating point data

Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, Phil C Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, Phil C Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA TO PACKED DECIMAL FORMAT

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh

decimal data type, decimal64 floating point format, decimal128 floating point format, decimal32 floating point format, decimal floating point, single precision floating point format, binary integer decimal, double precision floating point format, arithmet

Abstract

**2006**

Register Indirect Access of Program Floating Point Registers by Millicode

Steven R. Carlough, Mark S. Farrell, Eric M. Schwarz, Timothy J. Slegel, Charles F. Webb

millicode, operand, parsing, floating point, computer architecture, computer hardware, computer science

Abstract

Steven R. Carlough, Mark S. Farrell, Eric M. Schwarz, Timothy J. Slegel, Charles F. Webb

millicode, operand, parsing, floating point, computer architecture, computer hardware, computer science

Abstract

Common shift-amount calculation for binary and hex floating point

Son Dao Trong, Juergen Haess, Klaus Michael Kroener, Eric M. Schwarz

exponent bias, hexadecimal, operand, exponent, floating point, binary number, arithmetic, mathematics

Abstract

Son Dao Trong, Juergen Haess, Klaus Michael Kroener, Eric M. Schwarz

exponent bias, hexadecimal, operand, exponent, floating point, binary number, arithmetic, mathematics

Abstract

Multifunction hexadecimal instruction form

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, binary number, latency, architecture, parallel computing, computer science

Abstract

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, binary number, latency, architecture, parallel computing, computer science

Abstract

**2005**

Zero detect in partial sums while adding

Son Dao Trong, Mark Alan Erle, Bruce Martin Fleischer, Juergen Haess, Michael Robert Kelly, Klaus Michael Kroener, Martin Stanley Schmookler, Eric Mark Schwarz

wallace tree, floating point unit, leading zero, operand, bit array, adder, central processing unit, electronic circuit, theoretical computer science, control theory, mathematics

Abstract

Son Dao Trong, Mark Alan Erle, Bruce Martin Fleischer, Juergen Haess, Michael Robert Kelly, Klaus Michael Kroener, Martin Stanley Schmookler, Eric Mark Schwarz

wallace tree, floating point unit, leading zero, operand, bit array, adder, central processing unit, electronic circuit, theoretical computer science, control theory, mathematics

Abstract

Converting from decimal floating point into scaled binary coded decimal

Steven R. Carlough, Eric M. Schwarz, Sheryll H. Veneracion

decimal128 floating point format, decimal32 floating point format, decimal floating point, binary integer decimal, binary coded decimal, arithmetic, mathematics

Abstract

Steven R. Carlough, Eric M. Schwarz, Sheryll H. Veneracion

decimal128 floating point format, decimal32 floating point format, decimal floating point, binary integer decimal, binary coded decimal, arithmetic, mathematics

Abstract

System and method for a fused multiply-add dataflow with early feedback prior to rounding

Fleischer, Bruce and Haess, Juergen and Kroener, Michael and Montoye, Robert and Schmookler, Martin and Schwarz, Eric and Dao-Trong, Son

US Patent App. 11/055,232

Abstract

Fleischer, Bruce and Haess, Juergen and Kroener, Michael and Montoye, Robert and Schmookler, Martin and Schwarz, Eric and Dao-Trong, Son

US Patent App. 11/055,232

Abstract

System and method for performing floating point store folding

Juergen Haess, Michael Kroener, Dung Quoc Nguyen, Lawrence J. Powell, Eric M. Schwarz, Son Dao-Trong, Raymond C. Yeung

dead store, instruction register, load store architecture, control unit, register file, floating point, data type, computer hardware, real time computing, computer science

Abstract

Juergen Haess, Michael Kroener, Dung Quoc Nguyen, Lawrence J. Powell, Eric M. Schwarz, Son Dao-Trong, Raymond C. Yeung

dead store, instruction register, load store architecture, control unit, register file, floating point, data type, computer hardware, real time computing, computer science

Abstract

System and method for processing limited out-of-order execution of floating point loads

Juergen Haess, Michael Kroener, Dung Quoc Nguyen, Eric M. Schwarz, Son Dao-trong, Raymond C. Yeung

indirect branch, out of order execution, floating point, real time computing, parallel computing, computer science

Abstract

Juergen Haess, Michael Kroener, Dung Quoc Nguyen, Eric M. Schwarz, Son Dao-trong, Raymond C. Yeung

indirect branch, out of order execution, floating point, real time computing, parallel computing, computer science

Abstract

System and method for reduction of leading zero detect for decimal floating point numbers

Michael R. Kelly, Wen H. Li, Eric M. Schwarz, Wai Y. Wong

decimal floating point, numerical digit, arithmetic, mathematics

Abstract

Michael R. Kelly, Wen H. Li, Eric M. Schwarz, Wai Y. Wong

decimal floating point, numerical digit, arithmetic, mathematics

Abstract

System and method for converting binary to decimal

Steven R. Carlough, Bruce M. Fleischer, Wen H. Li, Eric M. Schwarz

find first set, bit numbering, bit length, bit plane, most significant bit, bit field, parity bit, least significant bit, arithmetic, mathematics

Abstract

Steven R. Carlough, Bruce M. Fleischer, Wen H. Li, Eric M. Schwarz

find first set, bit numbering, bit length, bit plane, most significant bit, bit field, parity bit, least significant bit, arithmetic, mathematics

Abstract

System and method for performing decimal floating point addition

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

decimal floating point, leading zero, absolute difference, operand, exponent, subtraction, adder, inequality, discrete mathematics, arithmetic, mathematics

Abstract

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

decimal floating point, leading zero, absolute difference, operand, exponent, subtraction, adder, inequality, discrete mathematics, arithmetic, mathematics

Abstract

System and method for performing decimal division

Steven R. Carlough, Paulomi Kadakia, Wen H. Li, Eric M. Schwarz

multiple, remainder, numerical digit, decimal, divisor, quotient, arithmetic, algebra, mathematics

Abstract

Steven R. Carlough, Paulomi Kadakia, Wen H. Li, Eric M. Schwarz

multiple, remainder, numerical digit, decimal, divisor, quotient, arithmetic, algebra, mathematics

Abstract

System and method for providing a decimal multiply algorithm using a double adder

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

running total, significant figures, numerical digit, decimal, least significant bit, adder, multiplication, multiplier, arithmetic, algorithm, mathematics

Abstract

Steven R. Carlough, Wen H. Li, Eric M. Schwarz

running total, significant figures, numerical digit, decimal, least significant bit, adder, multiplication, multiplier, arithmetic, algorithm, mathematics

Abstract

System and method for converting from scaled binary coded decimal into decimal floating point

Steven R. Carlough, Eric M. Schwarz, Sheryll H. Veneracion

decimal floating point, binary integer decimal, binary coded decimal, exponent, arithmetic, mathematics

Abstract

Steven R. Carlough, Eric M. Schwarz, Sheryll H. Veneracion

decimal floating point, binary integer decimal, binary coded decimal, exponent, arithmetic, mathematics

Abstract

System and method for converting from decimal floating point into scaled binary coded decimal

Steven R. Carlough, Eric M. Schwarz, Sheryll H. Veneracion

decimal128 floating point format, decimal32 floating point format, decimal floating point, binary integer decimal, binary coded decimal, arithmetic, mathematics

Abstract

Steven R. Carlough, Eric M. Schwarz, Sheryll H. Veneracion

decimal128 floating point format, decimal32 floating point format, decimal floating point, binary integer decimal, binary coded decimal, arithmetic, mathematics

Abstract

Fused multiply add split for multiple precision arithmetic

Guenter Gerwig, Eric M. Schwarz, Ronald M. Smith

multiply accumulate operation, operand, arithmetic logic unit, arbitrary precision arithmetic, architecture, arithmetic, parallel computing, mathematics

Abstract

Guenter Gerwig, Eric M. Schwarz, Ronald M. Smith

multiply accumulate operation, operand, arithmetic logic unit, arbitrary precision arithmetic, architecture, arithmetic, parallel computing, mathematics

Abstract

**2004**

Decimal rounding mode which preserves data information for further rounding to less precision

Eric M. Schwarz, Martin S. Schmookler

numerical digit, decimal, rounding, nice, least significant bit, truncation, arithmetic, mathematics

Abstract

Eric M. Schwarz, Martin S. Schmookler

numerical digit, decimal, rounding, nice, least significant bit, truncation, arithmetic, mathematics

Abstract

Floating point bypass register to resolve data dependencies in pipelined instruction sequences

Rainer Clemen, Guenter Gerwig, Jergen Haess, Harald Mielich, Bruce Martin Fleischer, Eric Mark Schwarz, Leon Jacob Sigal

US Patent App. 10/752,957

Rainer Clemen, Guenter Gerwig, Jergen Haess, Harald Mielich, Bruce Martin Fleischer, Eric Mark Schwarz, Leon Jacob Sigal

US Patent App. 10/752,957

**2003**

Multifunction hexadecimal instructions

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, binary number, latency, architecture, parallel computing, computer science

Abstract

Eric M. Schwarz, Ronald M. Smith

hexadecimal, dataflow, binary number, latency, architecture, parallel computing, computer science

Abstract

Decimal multiplication using digit recoding

Steven R. Carlough, Eric M. Schwarz

operand, numerical digit, decimal, least significant bit, adder, multiplication, microprocessor, arithmetic, computer hardware, mathematics

Abstract

Steven R. Carlough, Eric M. Schwarz

operand, numerical digit, decimal, least significant bit, adder, multiplication, microprocessor, arithmetic, computer hardware, mathematics

Abstract

**2002**

Two dimensional branch history table prefetching mechanism

Philip Emma, Klaus Getzlaff, Allan Hartstein, Thomas Pflueger, Thomas Puzak, Eric Schwarz, Vijayalakshmi Srinivasan

Philip Emma, Klaus Getzlaff, Allan Hartstein, Thomas Pflueger, Thomas Puzak, Eric Schwarz, Vijayalakshmi Srinivasan

**2001**

Floating-point multiplier for de-normalized inputs

Christopher A. Krygowski, Eric M. Schwarz

final product, exponent, normalization, multiplication, multiplier, floating point, discrete mathematics, mathematical analysis, mathematics

Abstract

Christopher A. Krygowski, Eric M. Schwarz

final product, exponent, normalization, multiplication, multiplier, floating point, discrete mathematics, mathematical analysis, mathematics

Abstract

Floating point unit for multiple data architectures

Christopher A. Krygowski, Eric M. Schwarz

decimal64 floating point format, half precision floating point format, ieee 754 1985, decimal128 floating point format, decimal32 floating point format, single precision floating point format, double precision floating point format, floating point unit, c

Abstract

Christopher A. Krygowski, Eric M. Schwarz

decimal64 floating point format, half precision floating point format, ieee 754 1985, decimal128 floating point format, decimal32 floating point format, single precision floating point format, double precision floating point format, floating point unit, c

Abstract

**1998**

Partitioning of binary quad word format multiply instruction on S/390 processor

Eric Mark Schwarz

half precision floating point format, quadruple precision floating point format, extended precision, single precision floating point format, ibm floating point architecture, binary integer decimal, significand, double precision floating point format, comp

Abstract

Eric Mark Schwarz

half precision floating point format, quadruple precision floating point format, extended precision, single precision floating point format, ibm floating point architecture, binary integer decimal, significand, double precision floating point format, comp

Abstract

Computer processor system for executing RXE format floating point instructions

Mark Anthony Check, Ronald M. Smith, John Stephen Liptay, Eric Mark Schwarz, Timothy John Slegel, Charles Franklin Webb

addressing mode, instruction register, instruction cycle, cache, cycles per instruction, instructions per cycle, out of order execution, central processing unit, computer hardware, real time computing, computer science

Abstract

Mark Anthony Check, Ronald M. Smith, John Stephen Liptay, Eric Mark Schwarz, Timothy John Slegel, Charles Franklin Webb

addressing mode, instruction register, instruction cycle, cache, cycles per instruction, instructions per cycle, out of order execution, central processing unit, computer hardware, real time computing, computer science

Abstract

Method and system for executing operations on denormalised numbers

Mark Anthony Check, Bruce Giamei, Christopher Krygowski, John Stephen Liptay, Eric Mark Schwarz

hazard, denormal number, instruction unit, execution unit, floating point unit, pipeline, control unit, floating point, real time computing, parallel computing, computer science

Abstract

Mark Anthony Check, Bruce Giamei, Christopher Krygowski, John Stephen Liptay, Eric Mark Schwarz

hazard, denormal number, instruction unit, execution unit, floating point unit, pipeline, control unit, floating point, real time computing, parallel computing, computer science

Abstract

Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code

Mark Anthony Check, Ronald M. Smith, John Stephen Liptay, Eric Mark Schwarz, Timothy John Slegel, Charles Franklin Webb

instruction register, instruction cycle, byte, cache, cycles per instruction, instructions per cycle, adder, central processing unit, computer hardware, parallel computing, computer science

Abstract

Mark Anthony Check, Ronald M. Smith, John Stephen Liptay, Eric Mark Schwarz, Timothy John Slegel, Charles Franklin Webb

instruction register, instruction cycle, byte, cache, cycles per instruction, instructions per cycle, adder, central processing unit, computer hardware, parallel computing, computer science

Abstract

Pipelined floating point stores

Christopher A. Krygowski, Eric Mark Schwarz

hazard, addressing mode, instruction register, instruction cycle, pipeline, control unit, bubble, central processing unit, real time computing, parallel computing, computer science

Abstract

Christopher A. Krygowski, Eric Mark Schwarz

hazard, addressing mode, instruction register, instruction cycle, pipeline, control unit, bubble, central processing unit, real time computing, parallel computing, computer science

Abstract

Method and system of rounding for quadratically converging division or square root

Eric Mark Schwarz

methods of computing square roots, remainder, rounding, square root, least significant bit, magnitude, floating point, binary number, discrete mathematics, mathematical optimization, mathematics

Abstract

Eric Mark Schwarz

methods of computing square roots, remainder, rounding, square root, least significant bit, magnitude, floating point, binary number, discrete mathematics, mathematical optimization, mathematics

Abstract

Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation

Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott

virtual address space, emulation, queue, preprocessor, synchronization, architecture, real time computing, computer science

Abstract

Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott

virtual address space, emulation, queue, preprocessor, synchronization, architecture, real time computing, computer science

Abstract

IEEE compliant floating point unit

Eric Mark Schwarz, Christopher A. Krygowski, Timothy John Slegel, David Frazelle McManigal, Mark Steven Farrell

millicode, ieee floating point, floating point unit, exception handling, floating point, binary number, engineering design process, detector, real time computing, computer science

Abstract

Eric Mark Schwarz, Christopher A. Krygowski, Timothy John Slegel, David Frazelle McManigal, Mark Steven Farrell

millicode, ieee floating point, floating point unit, exception handling, floating point, binary number, engineering design process, detector, real time computing, computer science

Abstract

**1997**

Method and system for executing denormalized numbers

Eric Mark Schwarz, Bruce Giamei, Christopher A. Krygowski, Mark Anthony Check, John Stephen Liptay

denormal number, instruction unit, execution unit, floating point unit, rounding, control unit, arithmetic underflow, floating point, real time computing, parallel computing, computer science

Abstract

Eric Mark Schwarz, Bruce Giamei, Christopher A. Krygowski, Mark Anthony Check, John Stephen Liptay

denormal number, instruction unit, execution unit, floating point unit, rounding, control unit, arithmetic underflow, floating point, real time computing, parallel computing, computer science

Abstract

Preprocessing of stored target routines for emulating incompatible instructions on a target processor

Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott

authorization, preprocessor, architecture, real time computing, computer science

Abstract

Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott

authorization, preprocessor, architecture, real time computing, computer science

Abstract

**1996**

Carry select and input select adder for late arriving data

Eric M. Schwarz, Tom McPherson, Chris Krygowski

serial binary adder, carry save adder, integrated circuit layout, operand, least significant bit, adder, logic synthesis, computation, electronic engineering, real time computing, parallel computing, computer science

Abstract

Eric M. Schwarz, Tom McPherson, Chris Krygowski

serial binary adder, carry save adder, integrated circuit layout, operand, least significant bit, adder, logic synthesis, computation, electronic engineering, real time computing, parallel computing, computer science

Abstract

Method and system of rounding for division or square root: eliminating remainder calculation

Thomas Joseph McPherson, Eric Mark Schwarz

methods of computing square roots, guard digit, remainder, rounding, square root, least significant bit, floating point, binary number, discrete mathematics, arithmetic, mathematics

Abstract

Thomas Joseph McPherson, Eric Mark Schwarz

methods of computing square roots, guard digit, remainder, rounding, square root, least significant bit, floating point, binary number, discrete mathematics, arithmetic, mathematics

Abstract

**1995**

Parallel calculation of exponent and sticky bit during normalization

Eric Mark Schwarz, Robert Michael Bunce, Leon Jacob Sigal, Hung Cai Ngo

sticky bit, multiplexing, exponent, dataflow, normalization, data flow diagram, discrete mathematics, mathematics

Abstract

Eric Mark Schwarz, Robert Michael Bunce, Leon Jacob Sigal, Hung Cai Ngo

sticky bit, multiplexing, exponent, dataflow, normalization, data flow diagram, discrete mathematics, mathematics

Abstract

Implementation of binary floating point using hexadecimal floating point unit

Eric Mark Schwarz, Charles Franklin Webb, Kai-Ann Ho

decimal64 floating point format, half precision floating point format, ieee 754 1985, decimal32 floating point format, single precision floating point format, ibm floating point architecture, ieee floating point, double precision floating point format, co

Abstract

Eric Mark Schwarz, Charles Franklin Webb, Kai-Ann Ho

decimal64 floating point format, half precision floating point format, ieee 754 1985, decimal32 floating point format, single precision floating point format, ibm floating point architecture, ieee floating point, double precision floating point format, co

Abstract

**1991**

Generalized 7/3 counters

Stamatis Vassiliadis, Eric M. Schwarz

row, matrix, arithmetic, mathematics

Abstract

Stamatis Vassiliadis, Eric M. Schwarz

row, matrix, arithmetic, mathematics

Abstract

**1989**

High speed parity prediction for binary adders

Eric Mark Schwarz, Stamatis Vassiliadis

byte, operand, adder, parity, binary number, theoretical computer science, parallel computing, mathematics

Abstract

Eric Mark Schwarz, Stamatis Vassiliadis

byte, operand, adder, parity, binary number, theoretical computer science, parallel computing, mathematics

Abstract

Twos complement multiplication with a sign magnitude multiplier

Stamatis Vassiliadis, Eric Mark Schwarz, Baik Moon Sung

two s complement, operand, multiplication, multiplier, magnitude, binary number, matrix, discrete mathematics, arithmetic, mathematics

Abstract

Stamatis Vassiliadis, Eric Mark Schwarz, Baik Moon Sung

two s complement, operand, multiplication, multiplier, magnitude, binary number, matrix, discrete mathematics, arithmetic, mathematics

Abstract

**1988**

More dynamic commands, multiple data more floating point pipeline

Eric Mark Schwarz, Stamatis Vassiliadis

floating point, computer hardware, computer science

Eric Mark Schwarz, Stamatis Vassiliadis

floating point, computer hardware, computer science

Dynamische Mehrbefehle-Mehrdaten-Mehrpipeline-Gleitpunkteinheit

Eric Mark Schwarz, Stamatis Vassiliadis

Eric Mark Schwarz, Stamatis Vassiliadis

Parity prediction for binary adders with selection

Stamatis Vassiliadis, Eric Mark Schwarz, Brice John Feal, Michael Putrino

byte, parity bit, integer, pi, adder, parity, binary number, arithmetic, algebra, mathematics

Abstract

Stamatis Vassiliadis, Eric Mark Schwarz, Brice John Feal, Michael Putrino

byte, parity bit, integer, pi, adder, parity, binary number, arithmetic, algebra, mathematics

Abstract

High speed parity prediction for binary adders using irregular grouping scheme

Stamatis Vassiliadis, Eric M. Schwarz

byte, operand, adder, parity, binary number, discrete mathematics, arithmetic, mathematics

Abstract

Stamatis Vassiliadis, Eric M. Schwarz

byte, operand, adder, parity, binary number, discrete mathematics, arithmetic, mathematics

Abstract

Overlapped multiple-bit scanning multiplication system with banded partial product matrix

Eric Mark Schwarz, Stamatis Vassiliadis

product term, sign extension, carry save adder, band matrix, bit field, row, multiplication, matrix, discrete mathematics, arithmetic, mathematics

Abstract

Eric Mark Schwarz, Stamatis Vassiliadis

product term, sign extension, carry save adder, band matrix, bit field, row, multiplication, matrix, discrete mathematics, arithmetic, mathematics

Abstract

Dynamic multiple instruction stream multiple data multiple pipeline floatingpoint unit

Eric Mark Schwarz, Stamatis Vassiliadis

orthogonal instruction set, classic risc pipeline, minimal instruction set computer, hazard, instruction register, instruction cycle, cycles per instruction, bubble, computer hardware, real time computing, computer science

Abstract

Eric Mark Schwarz, Stamatis Vassiliadis

orthogonal instruction set, classic risc pipeline, minimal instruction set computer, hazard, instruction register, instruction cycle, cycles per instruction, bubble, computer hardware, real time computing, computer science

Abstract

**1987**

Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures

Eric M. Schwarz, Stamatis Vassiliadis

orthogonal instruction set, classic risc pipeline, minimal instruction set computer, hazard, instruction register, instruction cycle, bubble, central processing unit, real time computing, parallel computing, computer science

Abstract

Eric M. Schwarz, Stamatis Vassiliadis

orthogonal instruction set, classic risc pipeline, minimal instruction set computer, hazard, instruction register, instruction cycle, bubble, central processing unit, real time computing, parallel computing, computer science

Abstract