Pouya Hashemi

contact information

Research Staff Member, Master Inventor, Exploratory Logic and Memory Devices
Thomas J. Watson Research Center, Yorktown Heights, NY USA
+1 dash

914

945

1958

links

more information

More information: Citation

2022

Double spin-torque magnetic tunnel junction devices for last-level cache applications
G. Hu, C. Safranski, J. Z. Sun, P. Hashemi, S. L. Brown, J. Bruley, L. Buzi, C. P. D'Emic, E. Galligan, M.G. Gottwald, O. Gunawan, J. Lee, S. Karimeddiny, P. L. Trouilloud, and D. C. Worledge
IEEE International Electron Device Meeting, 2022

Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions
C. Safranski, G. Hu, J. Z. Sun, P. Hashemi, S. L. Brown, L. Buzi, C. P. D' Emic, E. R. J. Edwards, E. Galligan, M. G. Gottwald, O. Gunawan, S. Karimeddiny, H. Jung, J. Kim, K. Latzko, P. L. Trouilloud, S. Zare, and D. C. Worledge
VLSI Tech. Symp., 2022

2021

Demonstration of nanosecond operation in stochastic magnetic tunnel junctions
C. Safranski, J. Kaiser, P. Trouilloud, P. Hashemi, G. Hu, J. Z Sun
Nano Letters21, 2040-2045, 2021
Abstract

2X reduction of STT-MRAM switching current using double spin-torque magnetic tunnel junction
G. Hu, G. Lauer, J. Z. Sun, P. Hashemi, C. Safranski, S. L. Brown, L. Buzi, E. R. J. Edwards, C. P. D'Emic, E. Galligan, M. G. Gottwald, O. Gunawan, H. Jung, J. Kim, K. Latzko, J. J. Nowak, P. L. Trouilloud, S. Zare, and D. C. Worledge
IEEE International Electron Device Meeting (IEDM '21), IEEE, 2021
Abstract

2020

Demonstration of narrow switching distributions in STT-MRAM arrays for LLC applications at 1x nm node
E. Edwards, G. Hu, S. Brown, C. D'Emic, M. Gottwald, P. Hashemi, H. Jung, J. Kim, G. Lauer, J. Nowak, J. Sun, T. Suwannasiri, P. Trouilloud, S. Woo, D. Worledge
IEEE International Electron Device Meeting (IEDM '20), IEEE, 2020
Abstract

2019

Materials and Process Innovations for High-Performance Strained Silicon-Germanium FinFETs with High Ge Content
T. Ando, P. Hashemi, E. A. Cartier, J. Bruley, and V. Narayanan
invited talk at the 2019 Materials Research Society (MRS) Spring Meeting
Abstract

Strain engineering for pFETs has been conventionally achieved by embedded SiGe source/drain to boost the transistor current drive and transconductance [1]. Historically, transconductance was monotonically improved by advancing the CMOS technology generations. However, this trend was no longer observed when FinFETs were introduced to the mainstream CMOS [2]. The deviation from the historical trend of transconductance is attributed to ineffectiveness of the embedded SiGe stressors (in spite of higher mobility near-(110) surfaces) and/or increased contribution of the S/D resistance as the contacted gate pitch size aggressively scales down. Strained SiGe (s-SiGe) channel, with built-in uniaxial compression, is a strong option to overcome this issue. In fact, SiGe channel has been utilized in CMOS industry as a knob to control the threshold voltage (Vth) and in part to boost the pFET reliability and transport [3]. Moreover, introduction of SiGe channel for planar pFET has improved reliability, resulting in further Equivalent-Oxide-Thickness (EOT) scaling over Si. For s-Si1-xGex FinFETs, choice of Ge content (x) has multipronged effects and it is not trivial. Adding more Ge can ideally build in more channel stress resulting increased hole mobility. On the other hand, fin height control due to the critical thickness constraints, process thermal budget, bandgap reduction and gate-induced drain leakage (GIDL) control remain challenging. From the view point of carrier transport, High-Ge-Content (HGC) s-SiGe FinFETs are of great interest for two reasons: (1) very high level of strain (~ 3GPa) can be achieved when lattice matched to Si [4]. (2) if strain-relaxed buffer (SRB) SiGe with moderate Ge % is used to tensily strain Si nFET, higher Ge is required to compressively strain the pFET [5]. The GIDL issue can be mitigated by operating the device at a lower VDD, i.e. below 0.6V, in accordance with logic roadmap [4]. Controlling the fin height, to be competitive with the state-of-the-art Si FinFETs, remains challenging. Above all, a major challenge is formation of gate stack and interface trap control which is more pronounced in HGC SiGe compared to Si and pure Ge. In this talk, materials and process innovations to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks on high-Ge-content SiGe channels will be discussed and their impact on key device characteristics will be presented. In particular, we review our recent progress in interfacial layer formation and passivation [6], high hole mobility and record performing short channel pMOS FinFETs. In addition, aggressive gate length scaling down to 15nm via an ultra-thin replacement metal-gate is demonstrated. [1] T. Ghani et al., IEDM, 2003, p. 197. [2] P. Hashemi, et al., IEDM, 2017, p. 824. [3] S. Krishnan et al., IEDM, 2011, p. 634. [4] P. Hashemi et al., IEDM, 2014, p. 402. [5] R. Xie et al., IEDM, 2016, p. 47. [6] P. Hashemi et al., VLSI Tech. Symp., 2017, p. 120.

Bias dependent conductance in CoFeB-MgO-CoFeB magnetic tunnel junctions as an indicator for electrode magnetic condition at barrier interfaces
J. Z. Sun, P. L. Trouilloud, G. P. Lauer, P. Hashemi
AIP Advances 9(1), 015002, AIP, 2019
Abstract

Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications
G. Hu, J. J. Nowak, M. G. Gottwald, S. L. Brown, B. Doris, C. P. D'Emic, P. Hashemi, D. Houssameddine, Q. He, D. Kim, J. Kim, C. Kothandaraman, G. Lauer, H K Lee, N. Marchack, M. Reuter, R. P. Robertazzi, J. Z. Sun, T. Suwannasiri, P. L. Trouilloud, and D. C. Worledge
IEEE International Electron Device Meeting (IEDM '19), IEEE, 2019

2018

A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation
J.-B. Yau, J. Cai, P. Hashemi, K. Balakrishnan, C. D'Emic, and T.H. Ning
Journal of Applied Physics 123(16), p. 161526, pp. 1-7, 2018

Advanced Replacement High-K/Metal Gate Stack Engineering for High-Performance Strained Silicon-Germanium FinFETs with High Ge Content
P. Hashemi, T. Ando, E. A. Cartier, J. Bruley, and V. Narayanan
ECS (Electrochemical Society) Transactions 86(7), 51-58, 2018

Toward SiGe Channel CMOS: Design of High Electron Mobility SiGe nFETs Outperforming Si
C.-H. Lee, R. G. Southwick III, S. Mochizuki, J. Li, X. Miao, M. Wang, R. Bao, I. Ok, T. Ando, P. Hashemi, D. Guo, V. Narayanan, N. Loubet, B. Haran, and H. Jagannathan
IEEE International Electron Device Meeting (IEDM' 18), IEEE, 2018

High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy
S. Lee, C. -W. Cheng, X. Sun, C. D' Emic, H. Miyazoe, M. Frank, J. Bruley, P. Hashemi, J. Ott, T. Ando, W. Spratt, G. Cohen, R. Bruce, M. Lofaro, J. Patel, H. Schmid, L. Czornomaz, V. Narayanan, R. T. Mo, and E. Leobandung
IEEE International Electron Device Meeting (IEDM'18), IEEE, 2018

SiGe Devices
P. Hashemi and T. Ando
A book chapter in "High Mobility Materials for CMOS Applications", pp. 205-229, Elsevier, Woodhead Publishing, 2018
Abstract

Advanced Replacement High-K/Metal Gate Stack Engineering for High-Performance Strained Silicon-Germanium Finfets with High Ge Content
P. Hashemi, T. Ando, E. A. Cartier, J. Bruley, V. Narayanan
invited talk at the AiMES/ECS International Symposium on SiGe, Ge, & Related Compounds: Materials, Processing, and Device, Electrochemical Society, 2018

Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring Epitaxially-Grown Emitter/Collector Regions
P. Hashemi, J.-B. Yau, K.K. Chan, T.H. Ning and G.G. Shahidi
IEEE Journal of the Electron Device Society6, 537-542, 2018
Abstract

2017

Three-dimensional monolithic integration of III-V and Si(Ge) FETs for hybrid CMOS and beyond
V. Deshpande, V. Djara, E. O'Connor, P. Hashemi, T. Morf, K. Balakrishnan, D. Caimi, M. Sousa, J. Fompeyrine, and L. Czornomaz
Japanese Journal of Applied Physics 56(4S), 04CA05, 2017

High Performance and Reliable Strained SiGe PMOS FinFETs Enabled by Advanced Gate Stack Engineering
P. Hashemi, T. Ando, E. A. Cartier, K.-L. Lee, J. Bruley, C.-H. Lee, and V. Narayanan
invited talk/paper at the IEEE International Electron Device Meeting (IEDM'17), pp. 824-827, IEEE Electron Device Society, 2017
Abstract

Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400C compatible p-MTJs
G. Hu, M. G. Gottwald, Q. He, J. H. Park, G. Lauer, J. J. Nowak, S. Brown, B. Doris, D. Edelstein, E. Evart, P. Hashemi, B. Khan, Y. H. Kim, C. Kothandaraman, N. Marchack, E. J. O' Sullivan, M. Reuter, R. P. Robertazzi, J. Z. Sun, T. Suwannasiri, P. L.
IEEE International Electron Device Meeting (IEDM'17), 2017

A Study of Process-Related Electrical Defects in SOI Lateral Bipolar Transistors Fabricated by Ion Implantation
J.-B. Yau, J. Cai, P. Hashemi, K. Balakrishnan, C. D' Emic, and T.H. Ning
Journal of Applied Physics, 2017

First Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring Epitaxially-Grown Emitter/Collector Regions
P. Hashemi, J.-B. Yau, K.K. Chan, T.H. Ning, G.G. Shahidi
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, IEEE, 2017

High Performance and Low Leakage Current InGaAs-on-Silicon FinFETs with 20 nm Gate Length
X. Sun, C. Demic, C.-W. Cheng, A. Majumdar, Y. Sun, E. Cartier, R. Bruce, M. Frank, H. Miyazoe, K.-T. Shiu, S. Lee, J. Rozen, J. Patel, T. Ando, W.-B. Song, M. Lofaro, M. Krishnan, B. Obrodovic, K.-T. Lee, H. Tsai, W.-E. Wang, W. Spratt, K. Chan, S. Lee, P. Hashemi, M. Khojaste
VLSI Tech. Symp., 2017

High Performance PMOS with Strained High-Ge-Content SiGe Fins for Advanced Logic Applications
P. Hashemi, T. Ando, K. Balakrishnan, S. Koswatta, K.-L. Lee, J. A. Ott, K. Chan, J. Bruley, S. U. Engelmann, V. Narayanan, E. Leobandung and R. T. Mo
invited talk at the International Symposium on VLSI Technology, Systems and Applications (2017 VLSI-TSA), Hsinchu, Taiwan, May, 2017

High Mobility High-Ge-Content SiGe PMOSFETs Using Al2O3/HfO2 Stacks with In-situ O3 Treatment
T. Ando, P. Hashemi, J. Bruley, J. Rozen, Y. Ogawa, S. Koswatta, K. K. Chan, E. A. Cartier, R. Mo, and V. Narayanan
IEEE Electron Device Letters 38(3), 303-305, 2017

DC and RF Characterization of InGaAs Replacement Metal Gate (RMG) nFETs on SiGe-OI FinFETs Fabricated by 3D Monolithic Integration
V. Deshpande, V. Djara, E. O'Connor, P. Hashemi, K. Balakrishnan, D. Caimi, M. Sousa, L. Czornomaz, J. Fompeyrine
Solid State Electronics128, 87-91, 2017

CMOS Device Technology Enablers and Challenges for 5nm node
P. Hashemi, T. B. Hook
2017 VLSI Technology Symp, Short Course on Technology enablers for 5nm and next wave of integration

High Performance and Record Subthreshold Swing Demonstration in Scaled RMG SiGe FinFETs with High-Ge-Content Channels Formed by 3D Condensation and a Novel Gate Stack Process
P. Hashemi, T. Ando, S. Koswatta, E. Cartier, J. A. Ott, C.-H. Lee*, K.-L. Lee, J. Bruley, M. F. Lofaro, K. K. Chan, S. U. Engelmann, E. Leobandung, V. Narayanan and R. T. Mo
VLSI Tech. Symp., 2017

2016

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations
P. Hashemi, K. Balakrishnan, T. Ando, K. L. Lee, R. T. Mo and E. Leobandung
ECS (Electrochemical Society) Transactions 75(8), 39-50, 2016

High mobility channel FinFET and Nanowire FET for new CMOS technology platform
P. Hashemi
invited talk at the International Symposium on Device Technology for Next-Generation Computing, 2016

InGaAs-on-Si(Ge) 3D Monolithic Integration for CMOS and More-than- Moore Technologies
V. Deshpande, V. Djara, T. Morf, P. Hashemi, E. O'Connor, K. Balakrishnan, D. Caimi, M. Sousa, J. Fompeyrine, L. Czornomaz
invited talk at the International Conference on Solid State Devices and Materials (SSDM 2016), IEEE, JSAP

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations
P. Hashemi, K. Balakrishnan, T. Ando, K.-L. Lee, R. T. Mo and E. Leobandung
invited talk at the 230th Electrochemical Society (ECS) International Symposium on SiGe, Ge, & Related Compounds: Materials, Processing, and Device, ECS, 2016

Strained SiGe FinFETs for High Performance CMOS
P. Hashemi
invited talk at the International Conference on Solid State Devices and Materials (SSDM 2016), IEEE, JSAP

Replacement High-K/Metal-Gate High-Ge-Content Strained SiGe FinFETs with High Hole Mobility and Excellent SS and Reliability at Aggressive EOT ~7A and Scaled Dimensions Down to Sub-4nm Fin Widths
P. Hashemi, T. Ando, K. Balakrishnan, E. Cartier, M. Lofaro, J. A. Ott, J. Bruley, K.-L. Lee, S. Koswatta, S. Dawes, J. Rozen, A. Pyzyna, K. Chan, S. U. Engelmann, D.-G. Park, V. Narayanan, R. T. Mo and E. Leobandung
VLSI Technology Symposium, IEEE, JSAP, 2016

Demonstration of Record SiGe Transconductance and Short-Channel Current Drive in High-Ge-Content SiGe PMOS FinFETs with Improved Junction and Scaled EOT
P. Hashemi, K.-L. Lee, T. Ando, K. Balakrishnan, J. A. Ott, S. Koswatta, S. U. Engelmann, D.-G. Park, V. Narayanan, R. T. Mo and E. Leobandung
VLSI Technology Symposium, IEEE, JSAP, 2016

FINFET Technology Featuring High Mobility SiGe Channel for 10nm and Beyond
D. Guo, G. Karve, G. Tsutsui, K. Y. Lim, R. Robison, T. Hook, R. Vega, D. Liu, S. Bedell, S. Mochizuki, F. Lie, K. Akarvardar, M. Wang, R. Bao, S. Burns, V. Chan, K. Cheng, J. Demarest, J. Fronheiser, P. Hashemi, J. Kelly, J. Li, N. Loubet, P. Montanini,
VLSI Technology Symposium, IEEE, JSAP, 2016
Abstract

High-k/Metal Gate Innovations in FinFET Era
T. Ando, B. Kannan, U. Kwon, P. Hashemi, T. Yamashitaand V. Narayanan
invited talk at the Material Research Society (MRS'16) spring meeting, Session EP11.07, MRS, 2016

High-Mobility High-Ge-Content SiGe PMOS FinFETs with Scaled EOT and Fin Dimensions for High-Performance Logic Applications
T. Ando and P. Hashemi
invited talk at the 7th International Symposium on Control of Semiconductor Interfaces (ISCSI-VII)/International SiGe Technology and Device Meeting (ISTDM 2016), IEEE

First RF Characterization of InGaAs Replacement Metal Gate (RMG) nFETs on SiGe-OI FinFETs Fabricated by 3D Monolithic Integration
V. Deshpande, V. Djara, E. O' Connor, D. Caimi, M. Sousa, L. Czornomaz J. Fompeyrine, P. Hashemi, K. Balakrishnan
Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2016), IEEE

2015

Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges
Pouya Hashemi, Karthik Balakrishnan, John A. Ott, Effendi Leobandung, Renee T. Mo, and Dae-Gyu Park
ECS Transactions 66(4), 17-30, Electrochemical Society (ECS), 2015

Advanced 3D Monolithic Hybrid CMOS with Sub-50 nm Gate Inverters Featuring Replacement Metal Gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs
V. Deshpande, V. Djara, E. O' Connor, P. Hashemi, K. Balakrishnan, M. Sousa, D. Caimi, A. Olziersky, L. Czornomaz and J. Fompeyrine
the 61st IEEE International Electron Device Meeting (IEDM '15), 2015

High-Mobility High-Ge-Content Si1-xGex-OI PMOS FinFETs with Fins Formed Using 3D Germanium Condensation with Ge Fraction up to x~ 0.7, Scaled EOT~8.5A and ~10nm Fin Width
P. Hashemi, T. Ando, K. Balakrishnan, J. Bruley, S. Engelmann, J. A. Ott, V. Narayanan, D.-G. Park, R.T. Mo, E. Leobandung
symposium highlight paper at the VLSI Technology Symposium, IEEE, 2015, IEEE, JSAP
(selected as the symposium highlight paper)

(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges
P. Hashemi, K. Balakrishnan, J.A. Ott, E. Leobandung, R.T. Mo, D.-G. Park
invited talk at the 227th Electrochemical Society (ECS) Meeting, ECS, 2015

(Invited) Strained Si1-xGex-on-Insulator FinFET: a P-FET Candidate for 10nm node and beyond
P. Hashemi, K. Balakrishnan, A. Majumdar, K. Chan, S.U. Engelmann, J.A. Ott, E. Leobandung, D.-G. Park
invited talk at the SEMICON Korea Tech. Symp., 2015

2014

First Demonstration of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS FinFETs with High Hole Mobility and Aggressively Scaled Fin Dimensions and Gate Lengths for High-Performance Applications
P. Hashemi, K. Balakrishnan, S. Engelmann, J. A. Ott, A. Khakifirooz, A. Baraskar, M. Hopstaken, J. S. Newbury, K. Chan, E. Leobandung, R. Mo and D.-G. Park
the 60th IEEE International Electron Device Meeting (IEDM '14), IEEE, 2014
Abstract Highlight Paper of the IEDM

Record Hole Mobility at High Vertical Fields in Planar Strained Germanium on Insulator With Asymmetric Strain
W. Chern, P. Hashemi, J. T. Teherani, T. Yu, D. A. Antoniadis, and J.L. Hoyt
IEEE Electron Device Letters 35(3), 309-311, 2014

Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations
D. Lu, P. Morin, B. Sahu, T. Hook, P. Hashemi, A. Scholze, B. Kim, P. Kerber, A. Khakifirooz, K. Rim, B. Doris and P. Oldiges
invited talk, the 226th Electrochemical Society (ECS) International Symposium on SiGe, Ge, & Related Compounds: Materials, Processing, and Device, ECS, 2014

Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond
P. Hashemi, K. Balakrishnan, A. Majumdar, A. Khakifirooz, W. Kim, A. Baraskar, L.A. Yang, K. Chan, S.U. Engelmann, J.A. Ott, D.A. Antoniadis, E. Leobandung, D.-G. Park
symposium highlight paper at the VLSI Technology Symposium, IEEE, 2014
(selected as symposium highlight paper)

Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node
P. Hashemi, K. Balakrishnan, A. Majumdar, M. Hopstaken, S.U. Engelmann, W. Kim, J.A. Ott, E. Leobandung and D.-G. Park
invited talk at the 226th Electrochemical Society (ECS) International Symposium on SiGe, Ge, & Related Compounds: Materials, Processing, and Device, ECS, 2014

Measurement and Analysis of Gate-Induced-Drain-Leakage in Short-Channel Strained Silicon Germanium-on-Insulator pMOS FinFETs
K. Balakrishnan, P. Hashemi, J. Ott, E. Leobandung and D.-G. Park
Device Research Conference, IEEE, 2014

Plasma Post-Oxidation for High Mobility Strained-Ge pFETs with Aggressively Scaled High-K Dielectrics
W. Chern, P. Hashemi, M. Kobayashi, D.-G. Park and J. L. Hoyt
the 226th Electrochemical Society (ECS) International Symposium on SiGe, Ge, & Related Compounds: Materials, Processing, and Device, ECS, 2014

Thin-film Si1-xGex HIT solar cells
S. Abdul Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, J. L. Hoyt
Solar Energy103, 154-159, 2014

2013

High-Performance Si1-xGex Channel on Insulator Trigate PFETs Featuring an Implant-Free Process and Aggressively-Scaled Fin and Gate Dimensions
P. Hashemi, M. Kobayashi, A. Majumdar, L. A. Yang, A. Baraskar, K. Balakrishnan, W. Kim, K. Chan, S. U. Engelmann, J. A. Ott, S. W. Bedell, C. E. Murray, S. Liang, R. H. Dennard, J. W. Sleight, E. Leobandung, and D.-G. Park
symposium highlight paper at the VLSI Technology Symposium, IEEE, 2013
(selected as symposium highlight paper)

Aggressively Scaled Strained Silicon Directly on Insulator (SSDOI) FinFETs
A. Khakifirooz, R. Sreenivasan, B.N. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E.C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S.M. Mignot, D. Lu, H. He, T. Yamashita, P. Morin, G. Tsutsui, C.-Y. Chen, V.S. Basker, T.E. Standaer, K.
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2013

Effect of Germanium Fraction on the Effective Minority Carrier Lifetime in Thin Film amorphous-Si/crystalline-Si1xGex/crystalline-Si Heterojunction Solar Cells
S. Abdul Hadi, P. Hashemi, N. DiLello, E. Polyzoeva, A. Nayfeh, and J. L. Hoyt
AIP Advancesvol. 3, 052119:1-6, AIP, 2013

2012

Effect of c-Si0.6Ge0.4 Thickness Grown by LPCVD on the Performance of Thin-Film a-Si/c-Si0.6Ge0.4/c-Si Heterojunction Solar Cells
S. Abdul Hadi, P. Hashemi, N. DiLello, A. Nayfeh, and J. L. Hoyt
2012 Material Research Society Symposium (MRS Spring 2012), Symposium V:Advanced Materials Processing for Scalable Solar-Cell Manufacturing II

Molecular Flash memories
S. Paydavosi, K. Aidala, P. Brown, P. Hashemi, G. J. Supran, J. L. Hoyt, and V. Bulovic
Electrochemical Society Meeting (ECS 2012), pp. 2839

Thin Film a-Si/c-Si1-xGex/c-Si Heterojunction Solar Cells with Ge Content Up To 56%
S. Abdul Hadi, P. Hashemi, N. DiLello, A. Nayfeh, and J. L. Hoyt
IEEE Photovoltaics Specialist Conference (PVSC), 2012

Strained Ge for Planar and Non-Planar p-MOSFETs
P. Hashemi, W. Chern and J.L. Hoyt
Internat ional Symposium on Development of Core Technologies for Green Nanoelectronics, 2012

High Performance Extremely Thin SOI (ETSOI) CMOS with Hybrid Si Channel NFET and Strained SiGe Channel PFET
K. Cheng, A. Khakifirooz, N. Loubet, S. Luning, T. Nagumo, M. Vinet, Q. Liu, A. Reznicek, T. Adam, S. Naczas, P. Hashemi, J. Kuss, J. Li, H. He, L. Edge, J. Gimbert, P. Khare, Y. Zhu, Z. Zhu, A. Madan, N. Klymko, S. Holmes, T. M. Levin, A. Hubbard, R. Joh
IEEE International Electron Device Meeting (IEDM), Session 18.1, 2012)

High Mobility High-k-All-Around Asymmetrically-Strained Germanium Nanowire Trigate p-MOSFETs
W. Chern, P. Hashemi, J. T. Teherani, T. Yu, Y. Dong, G. Xia, D. A. Antoniadis, and J.L. Hoyt
IEEE International Electron Device Meeting (IEDM) Session 16.5, 2012

Detection of Charge Storage on Molecular Thin Films of Tris (8-hydroxyquinoline) Aluminum (Alq3) by Kelvin Force Microscopy, a Candidate System for High Storage Capacity Memory Cells
S. Paydavosi, K.E. Aidala, P.R. Brown, P. Hashemi, G.J. Supran, T.P. Osedach, J.L. Hoyt, V. Bulovic
Nano Letters, American Chemical Society, 2012

High Hole-Mobility Strained-P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness
P. Hashemi, J.L. Hoyt
Electron Device Letters, IEEE 33(2), 173--175, IEEE, 2012

Ultra-thin strained-Ge pMOSFETs with high-K/metal gate and sub-1nm effective oxide thickness
P. Hashemi, W. Chern, H.-S. Lee, J. T. Teherani, Y. Zhu, J. Gonsalvez, G. G. Shahidi and J. L. Hoyt
IEEE Electron Device Letters 33(7), 943-945, 2012

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
A. Khakifirooz, K. Cheng, T. Nagumo, N. Loubet, T. Adam, A. Reznicek, J. Kuss, D. Shahrjerdi, R. Sreenivasan, S. Ponoth, H He, P. Kulkarni, Q. Liu, P. Hashemi, P. Khare, S. Luning, S. Mehta, J. Gimbert, Y. Zhu, Z. Zhu, J. Li, A. Madan, T. Levin, F. Monsie
VLSI Technology (VLSIT), 2012 Symposium on, pp. 117--118

2011

High Mobility Strained Ge Channels and Gate Dielectrics
J.L. Hoyt, P. Hashemi, H.-S. Lee, M.A. Bhuiyan, and D.A. Antoniadis
2011 Material Research Society Symposium (MRS 2011), Symp. P: Interface Engineering for Post-CMOS Emerging Channel Materials

Strained Nanowire MOSFETs
J. Hoyt, P. Hashemi, and W. Chern
220th Electrochemical Society (ECS), Session E9-ULSI Process Integration, 2011

High-density charge storage on molecular thin films-candidate materials for high storage capacity memory cells
S. Paydavosi, K. Aidala, P.R. Brown, P. Hashemi, T.P. Osedach, J.L. Hoyt, V. Bulovic
Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 24--4

a-Si/c-Si1- xGex/c-Si heterojunction solar cells
S.A. Hadi, A. Nayfeh, P. Hashemi, J. Hoyt
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pp. 191--194

Thin Film a-Si/c-SiGe/c-Si Heterojunction Solar Cells: Design and Material Quality Requirements
S.A. Hadi, P. Hashemi, A. Nayfeh, J. Hoyt
ECS, 2011

2010

Advanced Strained-Silicon and Core-Shell Si/Si1-xGex Nanowires for CMOS Transport Enhancement
P. Hashemi, C.D. Poweleit, M. Canonico, and J.L. Hoyt
218th Electrochemical Society (ECS) International Symposium on SiGe, Ge, & Related Compounds: Materials, Processing, and Device, Session 13.3, 2010

Increased critical thickness for high Ge-content strained SiGe-on-Si using selective epitaxial growth
M. Kim, P. Hashemi, J.L. Hoyt
Applied Physics Letters97, 262106, 2010

Low temperature growth of silicon dioxide using hydrogenation assisted nano-crystallization and plasma enhanced oxidation
N. Rouhi, B. Esfandyarpour, S. Mohajerzadeh, P. Hashemi, MD Robertson, K. Raffel
Journal of Non-Crystalline Solids 356(20-22), 1027--1031, Elsevier, 2010

Advanced Strained-Silicon and Core-Shell Si/SiGe Nanowires for CMOS Transport Enhancement
P. Hashemi, C. Poweleit, M. Canonico, J. Hoyt
ECS, 2010

Gate-all-around silicon nanowire MOSFETs: top-down fabrication and transport enhancement techniques
J.L. Hoyt, P. Hashemi, others
Ph.D. Thesis, 2010

Enhanced hole mobility in high Ge content asymmetrically strained-SiGe p-MOSFETs
L. Gomez, C. Ni ChleÌirigh, P. Hashemi, JL Hoyt
Electron Device Letters, IEEE 31(8), 782--784, IEEE, 2010

Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-Ðº/metal-gate: Effects of hydrogen thermal annealing and nanowire shape
P. Hashemi, J.T. Teherani, J.L. Hoyt
Electron Devices Meeting (IEDM), 2010 IEEE International, pp. 34--5

Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire metal-oxide-semiconductor-field-effect-transistors
P. Hashemi, M. Kim, J. Hennessy, L. Gomez, D.A. Antoniadis, J.L. Hoyt
Applied Physics Letters96, 063109, 2010

2009

Enhanced hole transport in short-channel strained-SiGe p-MOSFETs
L. Gomez, P. Hashemi, J.L. Hoyt
Electron Devices, IEEE Transactions on 56(11), 2644--2651, IEEE, 2009

Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter
P. Hashemi, L. Gomez, J.L. Hoyt
Electron Device Letters, IEEE 30(4), 401--403, IEEE, 2009

2008

Fabrication and Characterization of Suspended Uniaxial Tensile Strained-Si Nanowires for Gate-All-Around Nanowire n-MOSFETs
P. Hashemi, M. Canonico, J.K.W. Yang, L. Gomez, K.K. Berggren, J. Hoyt
ECS, 2008

Hole velocity enhancement in sub-100 nm gate length strained-SiGe channel p-MOSFETs on insulator
L. Gomez, P. Hashemi, JL Hoyt
SOI Conference, 2008. SOI. IEEE International, pp. 163--164

Silicon nano-crystalline structures fabricated by a sequential plasma hydrogenation and annealing technique
Y. Abdi, P. Hashemi, S. Mohajerzadeh, M. Jamei, MD Robertson, MJ Burns, JM MacLachlan
Thin Solid Films 516(10), 3172--3178, Elsevier, 2008

Performance enhancement in uniaxially tensile strained-Si gate-all-around nanowire n-MOSFETs
P. Hashemi, L. Gomez, M. Canonico, J.L. Hoyt
Device Research Conference, 2008, pp. 185--186

Fabrication of strained-Si/strained-Ge heterostructures on insulator
L. Gomez, M. Canonico, M. Kim, P. Hashemi, J.L. Hoyt
Journal of Electronic Materials 37(3), 240--244, Springer, 2008

Prospects for Top-Down Fabricated Uniaxial Strained Nanowire MOSFETs
J. Hoyt, P. Hashemi, L. Gomez
ECS, 2008

Fabrication and characterization of suspended uniaxial tensile strained-Si nanowires for gate-all-around n-MOSFETs
P. Hashemi, M. Canonico, JKW Yang, L. Gomez, KK Berggren, JL Hoyt
ECS Trans 16(10), 57--68, 2008

Electron transport in gate-all-around uniaxial tensile strained-Si nanowire n-MOSFETs
P. Hashemi, L. Gomez, M. Canonico, J.L. Hoyt
Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pp. 1--4

2007

Light emitting diodes on glass and silicon substrates fabricated using novel low temperature hydrogenation-assisted nano-crystallization of silicon thin films
B. Fallah-Azad, Y. Abdi, S. Mohajerzadeh, M. Jamei, P. Hashemi, MD Robertson
Semiconductor Device Research Symposium, 2007 International, pp. 1--2

Fabrication and Modeling of Gated Field-Emission Devices Using Carbon Nanotubes on Si Substrates
J. Koohsorkhi, S. Mohajerzadeh, Y. Abdi, P. Hashemi
MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS963, 112, Warrendale, Pa.; Materials Research Society; 1999, 2007

Silicon Nanocrystals Fabricated by a Novel Plasma Enhanced Hydrogenation Technique Suitable for Light Emitting Devices
M. Jamei, F. Karbassian, S. Mohajerzadeh, Y. Abdi, P. Hashemi, M. Robertson, S. Yuill
MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS958, 251, Warrendale, Pa.; Materials Research Society; 1999, 2007

Low Temperature High Quality Growth of Silicon-Dioxide Using Oxygenation of Hydrogenation-Assisted Nano-Structured Silicon Thin Films
N. Rouhi, B. Esfandyarpour, S. Mohajerzadeh, P. Hashemi, B. Hekmat-Shoar, M.D. Robertson
MRS Proceedings 989(1), Cambridge Univ Press, 2007

Asymmetric strain in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructures on insulator
P. Hashemi, L. Gomez, J.L. Hoyt, M.D. Robertson, M. Canonico
Applied Physics Letters91, 083109, 2007

Visible photoluminescence from a nanocrystalline porous silicon structure fabricated by a plasma hydrogenation and annealing method
Y. Abdi, M. Jamei, P. Hashemi, S. Mohajerzadeh, MD Robertson, MJ Burns, JM MacLachlan
Journal of applied physics101, 044309, 2007

2006

Hydrogenation-assisted nanocrystallization of amorphous silicon by radio-frequency plasma-enhanced chemical vapor deposition
P. Hashemi, Y. Abdi, S. Mohajerzadeh, J. Derakhshandeh, A. Khajooeizadeh, MD Robertson, RD Thompson, JM MacLachlan
Journal of applied physics100, 104320, 2006

2005

Metal Free Crystallization of Silicon by RF-PECVD Hydrogenation in Low Temperatures
P. Hashemi, A. Behnam, Y. Abdi, S. Mohajerzadeh, A. Khajooeizadeh and M. D. Robertson
12th Canadian Semiconductor Technology Conference (CSTC 2005)

Low Temperature Growth of Silicon Oxide Using a Novel Plasma Assisted Hydrogenation/Oxygenation Technique
Hashemi, A. Behnam, S. Mohajerzadeh, Y. Abdi, M.D. Robertson, J.C. Bennett, R. Thompson
12th Canadian Semiconductor Technology Conference (CSTC 2005)

Hydrogenation-Assisted Crystallization of Amorphous Silicon on Glass for Low Temperature Growth of Silicon Oxide Layers
P. Hashemi, Y. Abdi, S. Mohajerzadeh, and M. D. Robertson
21st International Conference on Amorphous and Nanocrystalline Semiconductors (ICANS 21), 2005

Encapsulated Vertically Grown Carbon Nano-Tubes for Submicron and Nano-Lithography
Y. Abdi, J. Koohsorkhi, P. Hashemi, S. Mohajerzadeh, H. Hoseinzadegan and L. Rezaee
Material Research Society Spring Meeting (MRS 2005)

Low Temperature Metal-Free Fabrication of polycrystalline Si and Ge TFTs by PECVD Hydrogenation
P. Hashemi, J. Derakhshandeh, B. Hekmatshoar, S. Mohajerzadeh, Y. Abdi, M.D. Robertson
Amorphous and Nanocrystalline Silicon Science and Technology-- 2005862, 659--664, Materials Research Society, 506 Keystone Drive, Warrendale, PA, 15086, USA,

Special Section on Analog Circuit and Device Technologies-Device-The Influence of the Stacked and Double Material Gate Structures on the Short Channel Effects in SOI MOSFETS
E. Fathi, A. Behnam, P. Hashemi, B. Esfandyarpour, M. Fathipour
IEICE Transactions on Electronics 88(6), 1122--1126, Tokyo, Japan: Institute of Electronics, Information and Communication Engineers, c1992-, 2005

Fabrication of nano-crystalline porous silicon on Si substrates by a plasma enhanced hydrogenation technique
Y. Abdi, P. Hashemi, F. Karbassian, FD Nayeri, A. Behnam, S. Mohajerzadeh, J. Koohsorhki, MD Robertson, E. Arzi
Amorphous and Nanocrystalline Silicon Science and Technology-2005862, 393--398, MATERIALS RESEARCH SOCIETY

Characterization of Low-Temperature Stress-Induced Crystallization of a-Si on Flexible Glass Substrates by Transmission Electron Microscopy and Raman Spectroscopy
P. Hashemi, J. Derakhshandeh, S. Mohajerzadeh, MD Robertson, JC Bennett, AS Arani, A. Afzali-Kusha
Microelectronics, 2005. ICM 2005. The 17th International Conference on, pp. 326--329

Light-emitting nano-porous silicon structures fabricated using a plasma hydrogenation technique
Y. Abdi, J. Derakhshandeh, P. Hashemi, S. Mohajerzadeh, F. Karbassian, F. Nayeri, E. Arzi, MD Robertson, H. Radamson
Materials Science and Engineering: B124, 483--487, Elsevier, 2005

2-D modeling of potential distribution and threshold voltage of short channel fully depleted dual material gate SOI MESFET
P. Hashemi, A. Behnam, E. Fathi, A. Afzali-Kusha, M. El Nokali
Solid-state electronics 49(8), 1341--1346, Elsevier, 2005

2004

The investigation of stress-assisted nickel-induced crystallization of silicon on glass by TEM and SEM
P. Hashemi, J. Derakhshandeh, S. Mohajerzadeh, and M. Robertson
31st Annual Meeting of the Microscopical Society of Canada, 2004

The influence of the stacked and double material gate structures on the short channel effects in SOI MOSFETs
A. Behnam, E. Fathi, P. Hashemi, B. Esfandiarpoor, M. Fathipour
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on, pp. 68--71

Two-dimensional analytical modeling and simulation of the potential and threshold voltage of a new fully depleted dual metal gate SOI MESFET
P. Hashemi, A. Behnam, E. Fathi, A. Afzali-Kusha
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on, pp. 372--375

Stress-assisted nickel-induced crystallization of silicon on glass
P. Hashemi, J. Derakhshandeh, S. Mohajerzadeh, M. Robertson, A. Tonita
Journal of Vacuum Science \& Technology A: Vacuum, Surfaces, and Films22, 966, 2004

2003

Stress-assisted nickel-induced crystallization of silicon on glass
P. Hashemi, A. Khajooeizadeh, S. Mohajerzadeh, J. Derakhshandeh, M. Robertson, and J.C. Bennett
11th Canadian Semiconductor Technology Conference (CSTC2003)

Pouya Hashemi gen_feedback_link(leftr, rightr);