Jaime H Moreno 
contact information
Distinguished ResearcherThomas J. Watson Research Center, Yorktown Heights, NY USA +1
9149454340
9149454340 links
Professional Associations
Professional Associations: ACM | ACM Distinguished Speaker | ACM SIGARCH | ACM SIGMICRO | IEEE | IEEE Computer Society2015
Active buffered memory
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, James A Kahle, Jaime H Moreno, Ravi Nair
US Patent 9,003,160
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, James A Kahle, Jaime H Moreno, Ravi Nair
US Patent 9,003,160
2012
Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry
Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Jaime H. Moreno, Ravi Nair, Daniel A. Prener
register file, processing element, multiple data, memory data register, memory buffer register, decoding methods, computer science, computer hardware
Abstract
Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Jaime H. Moreno, Ravi Nair, Daniel A. Prener
register file, processing element, multiple data, memory data register, memory buffer register, decoding methods, computer science, computer hardware
Abstract
Packed load/store with gather/scatter
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Jaime H Moreno, Ravi Nair, Daniel A Prener
US Patent App. 13/566,141
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Jaime H Moreno, Ravi Nair, Daniel A Prener
US Patent App. 13/566,141
Tree traversal in a memory device
James A Kahle, Jaime H Moreno, Ravi Nair
US Patent App. 13/688,530
James A Kahle, Jaime H Moreno, Ravi Nair
US Patent App. 13/688,530
Active memory device gather, scatter, and filter
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, James A Kahle, Jaime H Moreno, Ravi Nair
US Patent App. 13/674,520
Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, James A Kahle, Jaime H Moreno, Ravi Nair
US Patent App. 13/674,520
2011
Cache line replacement techniques allowing choice of LFU or MFU cache line replacement
Richard Edward Matick, Jaime H Moreno, Malcolm Scott Ware
US Patent 7,958,311
Richard Edward Matick, Jaime H Moreno, Malcolm Scott Ware
US Patent 7,958,311
2006
System and method for instruction memory storage and processing based on backwards branch control information
Sameh W Asaad, Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 7,130,963
Sameh W Asaad, Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 7,130,963
Apparatus and method for updating pointers for indirect and parallel register access
Shay Ben-David, Jeffrey Haskell Derby, Thomas W Fox, Jamie H Moreno, Fredy Daniel Neeser, Uzi Shvadron, Ayal Zaks
US Patent 7,017,028
Shay Ben-David, Jeffrey Haskell Derby, Thomas W Fox, Jamie H Moreno, Fredy Daniel Neeser, Uzi Shvadron, Ayal Zaks
US Patent 7,017,028
Cache with selective least frequently used or most frequently used cache line replacement
Richard Edward Matick, Jaime H Moreno, Malcolm Scott Ware
US Patent 7,133,971
Richard Edward Matick, Jaime H Moreno, Malcolm Scott Ware
US Patent 7,133,971
2005
System and method for VLSI visualization
D R Knebel, M A Lavin, J Moreno, S Polonsky, P N Sanda, S H Voldman
US Patent 6,895,372
D R Knebel, M A Lavin, J Moreno, S Polonsky, P N Sanda, S H Voldman
US Patent 6,895,372
Viterbi decoding for SIMD vector processors with indirect vector element access
Jaime Humberto Moreno, Fredy Daniel Neeser
US Patent 6,954,841
Jaime Humberto Moreno, Fredy Daniel Neeser
US Patent 6,954,841
SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath
Shay Ben-David, Jeffrey Haskell Derby, Jamie H Moreno, Fredy Daniel Neeser, Uzi Shvadron, Ayal Zaks, Victor Zyuban
US Patent 6,915,411
Shay Ben-David, Jeffrey Haskell Derby, Jamie H Moreno, Fredy Daniel Neeser, Uzi Shvadron, Ayal Zaks, Victor Zyuban
US Patent 6,915,411
Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width
Vinodh R Cuppu, Jaime H Moreno, Jude A Rivers
US Patent 6,948,051
Vinodh R Cuppu, Jaime H Moreno, Jude A Rivers
US Patent 6,948,051
2004
Method and apparatus for reducing encoding needs and ports to shared resources in a processor
Erik R Altman, Jaime H Moreno, Mayan Moudgill
US Patent 6,704,855
Erik R Altman, Jaime H Moreno, Mayan Moudgill
US Patent 6,704,855
Digital signal processor with SIMD organization and flexible data manipulation
Jaime H Moreno, Jeffrey Haskell Derby, Uzi Shvadron, Fredy Daniel Daniel Neeser, Victor Zyuban, Ayal Zaks, Shay Ben-david
US Patent 20,040,015,677
Jaime H Moreno, Jeffrey Haskell Derby, Uzi Shvadron, Fredy Daniel Daniel Neeser, Victor Zyuban, Ayal Zaks, Shay Ben-david
US Patent 20,040,015,677
Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching
Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 6,711,651
Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 6,711,651
Method and apparatus for memory prefetching based on intra-page usage history
Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 6,678,795
Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 6,678,795
2002
Apparatus for multiplication of data in two's complement and unsigned magnitude formats
Jaime Moreno, Uzi Shvadron, Ayal Zaks, Victor Zyuban
Jaime Moreno, Uzi Shvadron, Ayal Zaks, Victor Zyuban
2001
Method and apparatus for reducing logic activity in a microprocessor
Vinodh Cuppu, Jaime Moreno, Jude Rivers
Vinodh Cuppu, Jaime Moreno, Jude Rivers
1999
Apparatus region-based detection of interference among reordered memory operations in a processor
Jaime Humberto Moreno, Mavan Moudgill
US Patent 5,918,005
Jaime Humberto Moreno, Mavan Moudgill
US Patent 5,918,005
Object-code compatible representation of very long instruction word programs
Jaime Humberto Moreno
US Patent 5,951,674
Jaime Humberto Moreno
US Patent 5,951,674
1998
Branch on cache hit/miss for compiler-assisted miss delay tolerance
Charles Marshall Barton III, Pradeep Kumar Dubey, Jaime Humberto Moreno
US Patent 5,761,515
Charles Marshall Barton III, Pradeep Kumar Dubey, Jaime Humberto Moreno
US Patent 5,761,515
Method and apparatus for reordering memory operations in a processor
Jaime Humberto Moreno, Mayan Moudgill
US Patent 5,758,051
Jaime Humberto Moreno, Mayan Moudgill
US Patent 5,758,051
1997
Object code compatible representation of very long instruction word programs
Jaime Humberto Moreno
US Patent 5,669,001
Jaime Humberto Moreno
US Patent 5,669,001
Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
Mahmut K Ebcioglu, David A Luick, Jaime H Moreno, Gabriel M Silberman, Philip B Winterfield
US Patent 5,625,835
Mahmut K Ebcioglu, David A Luick, Jaime H Moreno, Gabriel M Silberman, Philip B Winterfield
US Patent 5,625,835
Projects and Groups
- 3D VLSI Integration
- Advanced Compiler Technologies
- Blue Gene Watson
- Blue Gene/Q Supercomputer Design
- Computer Architecture
- eLite DSP Project
- Future POWER Systems
- Low Power Processor Microarchitectures
- Main Memory Power, Performance, and Reliability Research
- Microarchitecture Exploration Toolset (MET)
- Power Reduction in High-Performance Microprocessors
- POWER7 (TM) Microprocessor Design
- Reliability and Power-Aware Microarchitectures
- Systems Technology and Microarchitecture
- The Cell Project
- VLIW Architecture
- WSC Cluster