Joseph N Kozhaya  Joseph N Kozhaya photo         

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Watson Data and AI Enablement Leader
  

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2020

PERSONALIZED VIDEO AND MEMORIES CREATION BASED ON ENRICHED IMAGES
Kozhaya Joseph, Kwatra Shikhar, Freed Andrew R, Allen Corville O
2020
Abstract   information retrieval, computer science, data matching


2014

PACMAN: Driving Nonuniform Clock Grid Loads for low-skew robust clock network
Zhou, Nancy Y and Restle, Phillip and Palumbo, Joseph and Kozhaya, Joseph and Qian, Haifeng and Li, Zhou and Alpert, Charles J and Sze, Cliff
System Level Interconnect Prediction (SLIP), 2014 ACM/IEEE International Workshop on, pp. 1--5
Abstract


2011

Myth busters: microprocessor clocking is from Mars, ASICs clocking is from Venus
Kozhaya, Joseph and Restle, Phillip and Qian, Haifeng
Proceedings of the International Conference on Computer-Aided Design, pp. 271--275, 2011
Abstract


2008

Power supply noise aware workload assignment for multi-core systems
Aida Todri, Malgorzata Marek-Sadowska, Joseph Kozhaya
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, pp. 330-337
Abstract   workload, multi core processor, integrated circuit design, digital electronics, electronic engineering, embedded system, computer science, capacitance, distance measurement, power grid


2006

ESD design automation & methodology to prevent CDM failures in 130 & 90 nm ASIC design systems
Ciaran J. Brennan, Joseph Kozhaya, Robert Proctor, Jeffrey Sloan, Shunhua Chang, James Sundquist, Terry Lowe, David Picozzi
Journal of Electrostatics 64(2), 112-127, 2006
Abstract   electronic design automation, design rule checking, automation, application specific integrated circuit, charged device model, chip, reliability engineering, electronic engineering, engineering, abstract design


2004

An electrically robust method for placing power gating switches in voltage islands
J.N. Kozhaya, L.A. Bakir
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), pp. 321-324
Abstract   power gating, switched mode power supply, low power electronics, clock gating, voltage optimisation, power semiconductor device, integrated circuit design, voltage, electrical engineering, electronic engineering, engineering

ESD design automation for a 90nm ASIC design system
C.J. Brennan, J. Kozhaya, R. Proctor, J. Sloan, Shunhua Chang, J. Sundquist, T. Lowe
2004 Electrical Overstress/Electrostatic Discharge Symposium, pp. 1-8
Abstract   integrated circuit design, electronic design automation, design rule checking, application specific integrated circuit, electrostatic discharge, chip, embedded system, electronic engineering, engineering, transient analysis

Power network analysis for ESD robustness in a 90nm ASIC design system
C.J. Brennan, J.N. Kozhaya, R.A. Proctor
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), pp. 247-250
Abstract   physical design, integrated circuit design, electrostatic discharge, circuit design, electronic design automation, circuit extraction, application specific integrated circuit, voltage drop, electronic engineering, engineering