Michael Gschwind  Michael Gschwind photo       

contact information

Chief Engineer, Machine Learning and Deep Learning
IBM TJ Watson Research Center


Professional Associations

Professional Associations:  ACM  |  ACM Distinguished Speaker   |  ACM SIGMICRO  |  Executive Board, ACM SIGMICRO  |  Fellow, IEEE  |  IEEE   |  IEEE Computer Society



Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
Robert J Blainey, Michael K Gschwind, James L McInnes, Michael R Meissner, Steven J Munroe
US Patent 8,607,211

Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals
Erik R Altman, Michael K Gschwind, Jude A Rivers, Sumedh W Sathaye, John-David Wellman, Victor V Zyuban
US Patent 8,589,662

Checkpointing in speculative versioning caches
Alexandre E Eichenberger, Alan Gara, Michael K Gschwind, Martin Ohmacht
US Patent 8,521,961


Structure for predictive decoding
Bartholomew Blaner, Michael K Gschwind
US Patent 8,095,777

System and method for speculative thread assist in a heterogeneous processing environment
Michael Norman Day, Michael Karl Gschwind, John Kevin Patrick O'brien, Kathryn O'brien
US Patent 8,214,808


Multi-addressable register file
M K Gschwind, B Olsson
US Patent 7,877,582

Multi-petascale highly efficient parallel supercomputer
Sameh Asaad, Ralph Bellofatto, Michael Blocksome, Matthias Blumrich, Peter Boyle, Jose R Brunheroto, Dong Chen, Chen-Yong Cher, George L Chiu, Norman Christ, others
US Patent App. 13/004,007


Vector Loads from Scattered Memory Locations
Alexandre E Eichenberger, Michael K Gschwind, Valentina Salapura
US Patent App. 12/876,432

Method and apparatus for profiling computer program execution
E R Altman, K Ebcioglu, M K Gschwind, S Sathaye
US Patent 7,735,072


Non-homogeneous multi-processor system with shared memory
E.R. Altman, P.G. Capek, M.K. Gschwind, C.R. Johns, H.P. Hofstee, M.E. Hopkins, J.A. Kahle, S.W. Sathaye, J.D. Wellman, R. Nair
US Patent 7,509,457

SIMD-RISC microprocessor architecture
M K Gschwind, H P Hofstee, M E Hopkins, J A Kahle
US Patent 7,496,673


Transient cache storage with discard function for disposable data
E R Altman, M K Gschwind, R K Montoye, J A Rivers, S W Sathaye, J D Wellman, V Zyuban
US Patent 7,461,209


B Blaner, M K Gschwind
US Patent App. 11/743,699



SIMD-RISC processor module
Michael Gschwind, Harm Hofstee, Charles Johns, James Kahle
US Patent App. 11/032,194

Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture
Erik Altman, Michael Gschwind, Daniel Prener, Jude Rivers, Sumedh Sathaye, John-David Wellman, Victor Zyuban
US Patent App. 11/047,983

Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions
E.R. Altman, P.G. Capek, M.K. Gschwind, H.P. Hofstee, J.A. Kahle, R. Nair, S.W. Sathaye, J.D. Wellman
US Patent 6,970,982

Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors
E R Altman, P G Capek, M Gschwind, H P Hofstee, J A Kahle, R Nair, S W Sathaye, J D Wellman
US Patent 6,907,477