Robert K. (Bob) Montoye

contact information

RSM
Thomas J. Watson Research Center, Yorktown Heights, NY USA
+1 dash

914

945

2816

links

Professional Associations

Professional Associations: ACM | IEEE

2016

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation
Arthur, John V and Brezzo, Bernard V and Chang, Leland and Friedman, Daniel J and Merolla, Paul A and Modha, Dharmendra S and Montoye, Robert K and Seo, Jae-sun and Tierno, Jose A
US Patent 9,373,073
Abstract

High-speed latch circuits by selective use of large gate pitch
Chang, Leland and Montoye, Robert K
US Patent App. 15/235,134
Abstract

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network
Arthur, John V and Brezzo, Bernard V and Chang, Leland and Friedman, Daniel J and Merolla, Paul A and Modha, Dharmendra S and Montoye, Robert K and Seo, Jae-sun and Tierno, Jose A
US Patent 9,239,984
Abstract

2015

Random number generation
Kozlosk, James R and Montoye, Robert K and Norel, Raquel and Rice, John J
US Patent 9,160,533
Abstract

Programmable regular expression and context free grammar matcher
Freitas, Richard F and Montoye, Robert K and Shinde, Rajendra
US Patent 9,093,151
Abstract

Writing scheme for phase change material-content addressable memory
Lam, Chung H and Li, Jing and Montoye, Robert K
US Patent 8,943,374
Abstract

2014

Method and apparatus for cache memory data processing
Cordero, Edgar R and Daly, David M and Montoye, Robert K and Sethuraman, Saravanan and Vidyapoornachary, Diyanesh B Chinnakkonda
US Patent App. 14/307,648
Abstract

Electronic synapses for reinforcement learning
Chang, Leland and Modha, Dharmendra S and Montoye, Robert K
US Patent 8,892,487
Abstract

Merging and Sorting Arrays on an SIMD Processor
Sreedhar, Dheeraj and Montoye, Robert and Derby, Jeffrey H
US Patent App. 14/219,391
Abstract

Shared parallel adder tree for executing multiple different population count operations
Blaner, Bartholomew and Iglehart, Todd R and Montoye, Robert K
US Patent 8,661,072
Abstract

Efficient voltage conversion
Chang, Leland and Montoye, Robert K and Seo, Jae-sun and Young, Albert M
US Patent App. 14/566,944
Abstract

Sort-merge-join on a large architected register file
Derby, Jeffrey H and Montoye, Robert Kevin and Sreedhar, Dheeraj
US Patent App. 14/488,827
Abstract

High-performance hash joins using memory with extensive internal parallelism
Derby, Jeffrey H and Johnson, Charles and Montoye, Robert K and Sreedhar, Dheeraj and VanderWiel, Steven P
US Patent App. 14/585,239
Abstract

Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming
Gopalakrishnan, Kailash and Lam, Chung H and Li, Jing and Montoye, Robert K
US Patent 8,842,491
Abstract

Multi-bit resistance measurement
Lam, Chung H and Li, Jing and Montoye, Robert K
US Patent 8,638,598
Abstract

Sense scheme for phase change material content addressable memory
Chang, Leland and Lam, Chung H and Li, Jing and Montoye, Robert K
US Patent 8,687,398
Abstract

Reconfigurable and customizable general-purpose circuits for neural networks
Brezzo, Bernard V and Chang, Leland and Esser, Steven K and Friedman, Daniel J and Liu, Yong and Modha, Dharmendra S and Montoye, Robert K and Rajendran, Bipin and Seo, Jae-sun and Tierno, Jose A and others
US Patent 8,856,055
Abstract

Low voltage signaling
Chang, Leland and Dennard, Robert H and Ji, Brian L and Luk, Wing K and Montoye, Robert K
US Patent 8,629,705
Abstract

2013

Writing scheme for phase change material-content addressable memory
Lam, Chung H and Li, Jing and Montoye, Robert K
US Patent 8,560,902
Abstract

Content addressable memories with wireline compensation
Lam, Chung Hon and Li, Jing and Montoye, Robert
US Patent 8,446,748
Abstract

Time division multiplexed limited switch dynamic logic
Chang, Leland and Montoye, Robert K and Nakamura, Yutaka
US Patent 8,604,832
Abstract

Switched capacitor voltage converters
Dennard, Robert H and Ji, Brian L and Montoye, Robert K
US Patent 8,395,438
Abstract

Enhanced data retention mode for dynamic memories
Reohr, William Robert and Montoye, Robert Kevin and Sperling, Michael A
US Patent 8,605,489
Abstract

2012

System and method for providing dynamic addressability of data elements in a register file with subword parallelism
Derby, Jeffrey H and Montoye, Robert K
US Patent App. 13/081,635
Abstract

Reconfigurable switched-capacitor voltage converter circuit, integrated circuit (ic) chip including the circuit and method of switching voltage on chip
Chang, Leland and Montoye, Robert and Seo, Jae-sun
US Patent App. 13/690,985
Abstract

Test structure for characterizing multi-port static random access memory and register file arrays
Chang, Leland and Kuang, Jente B and Montoye, Robert K and Ngo, Hung C and Nowka, Kevin J
US Patent 8,261,138
Abstract

Methods for generating code for an architecture encoding an extended register specification
Gschwind, Michael Karl and Montoye, Robert Kevin and Olsson, Brett and Wellman, John-David
US Patent 8,312,424
Abstract

Silicon carrier structure and method of forming same
Andry, Paul Stephen and Hofstee, Harm Peter and Katopis, George A and Knickerbocker, John Ulrich and Montoye, Robert K and Patel, Chirag S
US Patent 8,295,056
Abstract

Resistive memory devices having a not-and (NAND) structure
Breitwisch, Matthew J and Ditlow, Gary S and Franceschini, Michele M and Lastras-Montano, Luis A and Montoye, Robert K and Rajendran, Bipin
US Patent 8,107,276
Abstract

2011

Micro architecture for indirect access to a register file in a processor
Barak, Erez and Carro, Alejandro Rico and Derby, Jeffrey H and Golander, Amit and Heymann, Omer and Levison, Nadav and Manole, Sagi and Montoye, Robert K
US Patent App. 13/323,933
Abstract

Local Computation Logic Embedded in a Register File to Accelerate Programs
Bose, Pradip and Buyuktosunoglu, Alper and Derby, Jeffrey Haskell and Franceschini, Michele Martino and Montoye, Robert Kevin and Vega, Augusto J
US Patent App. 13/211,701
Abstract

Content addressable memory array
Chang, Leland and Ditlow, Gary S and Ji, Brian L and Montoye, Robert K
US Patent 8,054,662
Abstract

Content addressable memory reference clock
Chang, Leland and Ditlow, Gary S and Ji, Brian L and Montoye, Robert K
US Patent 7,948,782
Abstract

Content addressable memory array programmed to perform logic operations
Chang, Leland and Ditlow, Gary S and Ji, Brian L and Montoye, Robert K
US Patent 8,059,438
Abstract

2010

SerDes double rate bitline with interlock to block precharge capture
Chang, Leland and Ditlow, Gary and Montoye, Robert K and Storino, Salvatore N
US Patent 7,839,715
Abstract

Content addressable memory using phase change devices
Lam, Chung H and Ji, Brian L and Montoye, Robert K and Rajendran, Bipin
US Patent 7,751,217
Abstract

Hybrid static and dynamic sensing for memory arrays
Chang, Leland and Montoye, Robert K and Nakamura, Yutaka
US Patent 7,668,024
Abstract

Implementing instruction set architectures with non-contiguous register file specifiers
Gschwind, Michael Karl and Montoye, Robert Kevin and Olsson, Brett and Wellman, John-David
US Patent 7,793,081
Abstract

2009

System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation
Ditlow, Gary S and Montoye, Robert Kevin and Storino, Salvatore Nicholas
US Patent App. 12/427,218
Abstract

System for SIMD-oriented management of register maps for map-based indirect register-file access
Capek, Peter G and Derby, Jeffrey H and Montoye, Robert K
US Patent 7,631,167
Abstract

Sectored cache memory
Emma, Philip G and Montoye, Robert K and Srinivasan, Vijayalakshmi
US Patent 7,526,610
Abstract

Scannable limited switch dynamic logic (LSDL) circuit
Correale Jr, Anthony and Dick, Thomas A and Meier, Sven E and Montoye, Robert K
US Patent 7,501,850
Abstract

Content addressable memory array writing
Chang, Leland and Ditlow, Gary S and Ji, Brian L and Montoye, Robert K
US Patent App. 12/549,761
Abstract

2008

Method for SIMD-oriented management of register maps for map-based indirect register-file access
Capek, Peter G and Derby, Jeffrey H and Montoye, Robert K
US Patent 7,360,063
Abstract

Ultra high-speed Nor-type LSDL/Domino combined address decoder
Montoye, Robert Kevin and Nakamura, Yutaka
US Patent 7,349,288
Abstract

Shift-and-negate unit within a fused multiply-adder circuit
Datta, Ramyanshu and Montoye, Robert Kevin
US Patent 7,337,202
Abstract

Scanning latches using selecting array
Martin, Andrew Kenneth and McDowell, Chandler Todd and Montoye, Robert Kevin and Sawada, Jun
US Patent 7,383,480
Abstract

Transient cache storage with discard function for disposable data
Altman, Erik R and Gschwind, Michael Karl and Montoye, Robert Kevin and Rivers, Jude A and Sathaye, Sumedh Wasudeo and Wellman, John-David and Zyuban, Victor
US Patent 7,461,209
Abstract

Methods involving memory caches
Emma, Philip G and Montoye, Robert K and Srinivasan, Vijayalakshmi
US Patent 7,472,226
Abstract

2007

Computing carry-in bit to most significant bit carry save adder in current stage
Belluomini, Wendy A and Datta, Ramyanshu and Kuang, Jente Benedict and McDowell, Chandler T and Montoye, Robert K and Ngo, Hung C
US Patent 7,216,141
Abstract

4-to-2 carry save adder using limited switching dynamic logic
Belluomini, Wendy A and Datta, Ramyanshu and McDowell, Chandler T and Montoye, Robert K and Ngo, Hung C
US Patent 7,284,029
Abstract

Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock
Belluomini, Wendy Ann and Montoye, Robert Kevin and Saha, Aniket Mukul
US Patent 7,282,960
Abstract

Methods and arrangements to adjust a duty cycle
Agarwal, Kanak B and Montoye, Robert K
US Patent 7,298,193
Abstract

High speed latch circuits using gated diodes
Luk, Wing K and Chang, Leland and Dennard, Robert H and Montoye, Robert
US Patent 7,242,629
Abstract

Dynamic memory architecture employing passive expiration of data
Emma, Philip George and Montoye, Robert Kevin and Reohr, William Robert
US Patent 7,290,203
Abstract

2006

Method and apparatus for performing bit-aligned permute
Datta, Ramyanshu and Montoye, Robert Kevin
US Patent 7,014,122
Abstract

Method and apparatus for low overhead circuit scan
Belluomini, Wendy Ann and Martin, Andrew K and McDowell, Chandler Todd and Montoye, Robert Kevin
US Patent 7,047,468
Abstract

Controlled load limited switch dynamic logic circuitry
Ngo, Hung C and Sivagnaname, Jayakumaran and Nowka, Kevin J and Montoye, Robert K
US Patent 7,129,754
Abstract

Sense amplifier circuits and high speed latch circuits using gated diodes
Luk, Wing K and Chang, Leland and Dennard, Robert H and Montoye, Robert
US Patent 7,116,594
Abstract

Memory cell having improved read stability
Chang, Leland and Dennard, Robert H and Montoye, Robert Kevin
US Patent 7,106,620
Abstract

2005

Silicon chip carrier with conductive through-vias and method for fabricating same
Edelstein, Daniel and Andry, Paul and Buchwalter, Leena and Casey, Jon and Goma, Sherif and Horton, Raymond and Hougham, Gareth and Lane, Michael and Liu, Xiao and Patel, Chirag and others
US Patent App. 11/242,221
Abstract

Apparatus for increasing addressability of registers within a processor
Capek, Peter and Montoye, Robert
US Patent App. 11/065,602
Abstract

System and method for a fused multiply-add dataflow with early feedback prior to rounding
Fleischer, Bruce and Haess, Juergen and Kroener, Michael and Montoye, Robert and Schmookler, Martin and Schwarz, Eric and Dao-Trong, Son
US Patent App. 11/055,232
Abstract

Variable pulse width and pulse separation clock generator
Ngo, Hung Cai and Belluomini, Wendy Ann and Montoye, Robert Kevin
US Patent 6,891,399
Abstract

Limited switch dynamic logic selector circuits
Belluomini, Wendy A and Montoye, Robert K and Ngo, Hung C
US Patent 6,873,188
Abstract

Integrated circuit chip package with formable intermediate 3D wiring structure
Emma, Philip G and Montoye, Robert K and Zingher, Arthur R
US Patent 6,952,352
Abstract

2004

Cache memory system for selectively storing directory information for a higher level cache in portions of a lower level cache
Charney, Mark Jay and Emma, Philip George and Montoye, Robert K and Zingher, Arthur R
US Patent 6,763,432
Abstract

Limited switch dynamic logic circuit
Belluomini, Wendy A and Montoye, Robert K and Ngo, Hung C
US Patent 6,690,204
Abstract

2003

Fast, symmetrical XOR/XNOR gate
Boerstler, David William and Carballo, Juan Antonio and Montoye, Robert Kevin
US Patent 6,573,758
Abstract

Spacer-connector stud for stacked surface laminated multi-chip modules and methods of manufacture
Cohn, David Leslie and McBride, Dennis Jay and Montoye, Robert Kevin
US Patent 6,667,555
Abstract

Spacer-connector stud for stacked surface laminated multichip modules and methods of manufacture
Cohn, David Leslie and McBride, Dennis Jay and Montoye, Robert Kevin
US Patent 6,537,852
Abstract

Method and apparatus for improved compression and decompression
Auerbach, Daniel Jonathan and Kemp, Timothy Michael and Montoye, Robert Kevin and Palmer, John Davis
US Patent 6,618,506
Abstract

Circuits and systems for limited switch dynamic logic
Ngo, Hung Cai and Belluomini, Wendy Ann and Montoye, Robert Kevin
US Patent 6,650,145
Abstract

Multi-chip integrated circuit module
Hofstee, Harm Peter and Montoye, Robert Kevin and Sprogis, Edmund Juris
US Patent 6,507,115
Abstract

2002

Multiphase clock generator
Boerstler, David William and Montoye, Robert Keven and Nowka, Kevin John
US Patent 6,441,667
Abstract

Mobile modular computer
Ocheltree, Kenneth and Anzai, Masato and Dono, Nicholas and Hino, Akira and Imai, Toshitaka and Kawano, Seiichi and Noda, Shinsuke and Mandese, Ernest and Mito, Toshitsugu and Moulic, James and others
US Patent App. 10/323,197
Abstract

2001

Method and system for managing innovation by encouraging reusability and subsequent reuse of design components
Belluomini, Wendy and Carballo, Juan-Antonio and Donofrio, Nicholas and Montoye, Robert and Nowka, Kevin
US Patent App. 09/891,343
Abstract

Methods for caching cache tags
Chang, Albert and Charney, Mark and Montoye, Robert K and Puzak, Thomas R
US Patent 6,311,253
Abstract

Method of fabricating an electronic package with interconnected chips
Horton, Raymond Robert and Lanzetta, Alphonso Philip and Milewski, Joseph Maryan and Mok, Lawrence S and Montoye, Robert Kevin and Shaukatulla, Hussain
US Patent 6,306,686
Abstract

Processor transparent on-the-fly instruction stream decompression
Auerbach, Daniel Jonathan and Kemp, Timothy Michael and Montoye, Robert Kevin and Palmer, John Davis
US Patent 6,199,126
Abstract

Portable computing device having a display movable thereabout
Emma, Philip George and Montoye, Robert Kevin
US Patent 6,262,885
Abstract

Electronic package with interconnected chips
Horton, Raymond Robert and Lanzetta, Alphonso Philip and Milewski, Joseph Maryan and Mok, Lawrence S and Montoye, Robert Kevin and Shaukatulla, Hussain
US Patent 6,326,696
Abstract

1998

Method and system for compressing microcode to be executed within a data processing system
Auerbach, Daniel Jonathan and Craft, David John and Montoye, Robert Kevin
US Patent 5,745,058
Abstract

1997

Fast swing-limited pullup circuit
Shenoy, Michael A and Williams, Ted and Montoye, Robert K
US Patent 5,619,153
Abstract

1995

Testable latch self checker
Montoye, Robert K
US Patent 5,381,418
Abstract

1993

Tri state buffer circuit for dual power system
Kitahara, Takeshi and Montoye, Robert K
US Patent 5,266,849
Abstract

Floating point arithmetic two cycle data flow
Cocanougher, Daniel and Montoye, Robert K and Nguyenphu, Myhong and Runyon, Stephen L
US Patent 5,212,662
Abstract

1991

Floating point arithmetic two cycle data flow
Cocanougher, Daniel and Montoye, Robert K and Nguyenphu, Myhong and Runyon, Stephen L
US Patent 4,999,802
Abstract

1990

Apparatus for determining if there is a loss of data during a shift operation
Cook, Peter W and Montoye, Robert K
US Patent 4,931,970
Abstract

Partial decode shifter/rotator
Cook, Peter W and Montoye, Robert K
US Patent 4,931,971
Abstract

Leading 0/1 anticipator (LZA)
Hokenek, Erdem and Montoye, Robert K
US Patent 4,926,369
Abstract

Floating point unit for calculating A= XY+ Z having simultaneous multiply and add
Montoye, Robert K and Cocke, John
US Patent 4,969,118
Abstract

1987

Test circuit for differential cascode voltage switch
Kirkpatrick, Edward S and Kronstadt, Eric P and Montoye, Robert K and Wilcke, Winfried W
US Patent 4,656,417
Abstract

Technical Areas

Computer Systems Design

Robert K. (Bob) Montoye gen_feedback_link(leftr, rightr);