Pradip Bose  Pradip Bose photo         

contact information

Distinguished Research Staff Member and Manager of Efficient & Resilient Systems
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash3478

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Professional Associations

Professional Associations:  ACM  |  ACM SIGARCH  |  ACM SIGMICRO  |  IEEE  |  IEEE Computer Society


2014

Cross-layer system resilience at affordable power
Meeta S Gupta, Jude A Rivers, Liang Wang, Pradip Bose
Reliability Physics Symposium, 2014 IEEE International, pp. 2B--1

Resilience and Real-Time Constrained Energy Optimization in Embedded Processor Systems
Liang Wang, Jude A Rivers, Meeta S Gupta, Augusto J Vega, Alper Buyuktosunoglu, Pradip Bose, Kevin Skadron
Proc. of 10th Workshop on Silicon Errors in Logic--System Effects (SELSE-10), 2014


2013

SMT switch: Software Mechanisms for Power Shifting
Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose
Computer Architecture Letters 12(2), 67--70, IEEE, 2013

Crank it up or dial it down: coordinated multiprocessor frequency and folding control
Augusto Vega, Alper Buyuktosunoglu, Heather Hanson, Pradip Bose, Srinivasan Ramani
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 210--221, 2013

SMT-centric power-aware thread placement in chip multiprocessors
Augusto Vega, Alper Buyuktosunoglu, Pradip Bose
Parallel Architectures and Compilation Techniques (PACT), 2013 22nd International Conference on, pp. 167--176

Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems
Ramon Bertran, Yutaka Sugawara, Hans Jacobson, Alper Buyuktosunoglu, Pradip Bose
IBM Journal of Research and Development 57(1/2), 4--1, IBM, 2013

SMT malleability in IBM POWER5 and POWER6 processors
Alessandro Morari, Carlos Boneti, Francisco J Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero
Computers, IEEE Transactions on 62(4), 813--826, IEEE, 2013


2012

Energy-secure computing
Pradip Bose
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, pp. 1--2

Preface
Pierre Bonami, Leo Liberti, Andrew J. Miller, Annick Sartenaer
Math. Program. 136(2), 229--231, 2012

Architectural perspectives of future wireless base stations based on the IBM PowerENâ„¢ processor
Augusto Vega, Pradip Bose, Alper Buyuktosunoglu, Jeff Derby, Michele Franceschini, Charles Johnson, Robert Montoye
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pp. 1--10

Guarded power gating in a multi-core setting
Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram
Computer Architecture, pp. 198--210, 2012

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
Ramon Bertran, Alper Buyuktosunoglu, Meeta S Gupta, Marc Gonzalez, Pradip Bose, Barcelona Supercomputing Center
Internation Symposium on Microarchitecture (MICRO), pp. 199--211, 2012

Power Management of Multi-Core Chips: Challenges and Pitfalls
Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta S. Gupta, Michael B. Healy, Hans Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger
Design, Automation & Test in Europe Conference & Exhibition, pp. 977--982, 2012

Making data prefetch smarter: Adaptive prefetching on POWER7
Victor Jim\'enez, Roberto Gioiosa, Francisco J Cazorla, Alper Buyuktosunoglu, Pradip Bose, Francis P O'Connell
Proceedings of the 21st international conference on Parallel architectures and compilation techniques, pp. 137--146, 2012

Power-aware thread placement in SMT/CMP architectures
Augusto Vega, Pradip Bose, Alper Buyuktosunoglu
Proc. of the 4th Workshop on Energy Efficient Design (WEED), Portland, OR, USA, 2012

Energy-aware meeting scheduling algorithms for smart buildings
Abhinandan Majumdar, David H Albonesi, Pradip Bose
Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Buildings, pp. 161--168, 2012


2011

Characterizing Power and Temperature Behavior of POWER6-Based System
Victor Jimenez, Fran J Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, JESTCS, Volume 1 Issue 3, September 1(3), 228--241, IEEE, 2011

Abstraction and microarchitecture scaling in early-stage power modeling
Hans Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard Eickemeyer
High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, pp. 394--405

Energy-aware accounting and billing in large-scale computing facilities
Victor Jimenez, Roberto Gioiosa, Francisco J Cazorla, Mateo Valero, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose
IEEE Micro pp. 3, 60--71, IEEE, 2011

Introducing the adaptive energy management features of the POWER7 chip
Michael Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J Drake, Lorena Pesantez, Tilman Gloekler, Jose A Tierno, Pradip Bose, others
IEEE Micro 31(2), 60--75, 2011

Adaptive energy-management features of the IBM POWER7 chip
Michael Floyd, Malcolm Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, Juan C Rubio, Birgit Schubert, Bruno Spruth, others
IBM Journal of Research and Development 55(3), 8--1, IBM, 2011


2010

Power and thermal characterization of POWER6 system
Victor Jim\'enez, Francisco J Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose
Proceedings of the 19th international conference on Parallel architectures and compilation techniques, pp. 7--18, 2010

Trends and Techniques for Energy Efficient Architectures
Victor Jimenez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero
In Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, pp. 276-279, pp. 276--279, 2010

Power-efficient, Reliable Microprocessor Architectures: Modeling and Design Methods
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger and Victor V. Zyuban
In Proceedings of IEEE International Symposium, GLSVLSI, pp. 299 - 304, pp. 299--304, IEEE, ACM, 2010
Abstract

Performance and power evaluation of an in-line accelerator
Alejandro Rico, Jeff H Derby, Robert K Montoye, Timothy H Heil, Chen-Yong Cher, Pradip Bose
Proceedings of the 7th ACM international conference on Computing frontiers, pp. 81--82, 2010


2009

Dynamic power gating with quality guarantees
Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J Sorin
Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, pp. 377--382

Tribeca: Design for PVT Variations with Local Recovery and Fine-grained Adaptation
Meeta S. Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei and David Brooks
International Symposium on Microarchitecture (MICRO-42), pp. 435--446, 2009

Multicore power management: Ensuring robustness via early-stage formal verification
Anita Lungu, Pradip Bose, Daniel J Sorin, Steven German, Geert Janssen
Formal Methods and Models for Co-Design, 2009. MEMOCODE'09. 7th IEEE/ACM International Conference on, pp. 78--87

Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design
Yu Cao, Jim Tschanz, Pradip Bose
Design \& Test of Computers, IEEE 26(6), 6--7, IEEE, 2009


2008

Metrics for architecture-level lifetime reliability analysis
Pradeep Ramachandran, Sarita V Adve, Pradip Bose, Jude A Rivers
Performance Analysis of Systems and software, 2008. ISPASS 2008. IEEE International Symposium on, pp. 202--212

Online estimation of architectural vulnerability factor for soft errors
Xiaodong Li, Sarita V Adve, Pradip Bose, Jude A Rivers
Computer Architecture, 2008. ISCA'08. 35th International Symposium on, pp. 341--352

A proactive wearout recovery approach for exploiting microarchitectural redundancy to extend cache SRAM lifetime
Jeonghee Shin, Victor Zyuban, Pradip Bose, Timothy M Pinkston
ACM SIGARCH Computer Architecture News, pp. 353--362, 2008

Phaser: Phased methodology for modeling the system-level effects of soft errors
JA Rivers, P Bose, P Kudva, J D Wellman, PN Sanda, EH Cannon, LC Alves
IBM Journal of Research and Development 52(3), 293--306, IBM, 2008


2007

Architecture-level soft error analysis: Examining the limits of common assumptions
Xiaodong Li, Sarita V Adve, Pradip Bose, Jude A Rivers
Dependable Systems and Networks, 2007. DSN'07. 37th Annual IEEE/IFIP International Conference on, pp. 266--275

Hotspot-limited microprocessors: Direct temperature and power distribution measurements
Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, and Jamil Wakil
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 1, JANUARY 2007 V2(1), 56--65, IEEE

A framework for architecture-level lifetime reliability modeling
Jeonghee Shin, Victor Zyuban, Zhigang Hu, Jude A Rivers, Pradip Bose
Dependable Systems and Networks, 2007. DSN'07. 37th Annual IEEE/IFIP International Conference on, pp. 534--543

Performance modeling for early analysis of multi-core systems
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han
Proceedings of the 5th IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS), pp. 209--214, 2007

Evaluating design tradeoffs in on-chip power management for CMPs
J Sharkey, A Buyuktosunoglu, P Bose
Proceedings of the 2007 international symposium on Low power electronics and design, pp. 49

Thermal-aware task scheduling at the system software level
J Choi, C Y Cher, H Franke, H Hamann, A Weger, P Bose
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED), pp. 218, ACM
Abstract


2006

Measuring the impact of microarchitectural ideas
Pradip Bose
IEEE Micro 26(1), 5--6, IEEE Computer Society, 2006

Pre-silicon modeling and analysis: Impact on real design
Pradip Bose
IEEE Micro 26(4), 3--3, IEEE Computer Society, 2006

Looking briefly back, and then forward...
Pradip Bose
Micro, IEEE 26(6), 8--9, IEEE, 2006

Metrics for lifetime reliability
Pradeep Ramachandran, Sarita V Adve, Pradip Bose, Jude A Rivers, Jayanth Srinivasan
2006 - ideals.illinois.edu

Workload characterization: A key aspect of microarchitecture design
Pradip Bose
IEEE Micro 26(2), 5--6, IEEE Computer Society, 2006


Temperature Management: Investigating the Effects of Task Scheduling on Thermal Behavior
Eren Kursun, Chen Yong Cher, Alper Buyuktosunoglu, Pradip Bose
In Proceedings of International Symposium on Computer Architecture, Temperature-Aware Computer Systems , 2006

An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget
C Isci, A Buyuktosunoglu, C Y Cher, P Bose, M Martonosi
39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 347--358, 2006


2005


High performance at affordable power
Pradip Bose
Micro, IEEE 25(5), 5--5, IEEE, 2005

Tutorial: Power-aware, reliable microprocessor design
Pradip Bose
VLSI Design, 2005. 18th International Conference on, pp. 3

EIC's Message: Integrated microarchitectures
Pradip Bose
IEEE MICRO 25(3), 0005--6, IEEE Computer Society, 2005

Guest Editors' Introduction: Energy-Efficient Design
Kunio Uchiyama, Pradip Bose
Micro, IEEE 25(5), 6--9, IEEE, 2005

Power-aware microarchitectures: Design, modeling and metrics
Pradip Bose
Proceedings of the 17th Symposium on High Performance Chips (HotChip), Tutorial Note, pp. 14--16, 2005

EIC's Message: Variation-tolerant design
Pradip Bose
IEEE MICRO 25(2), 0005, IEEE Computer Society, 2005

Scaling of Architecture Level Soft Error Rates for Superscalar Processors
Xiaodong Li, Sarita V Adve, Pradip Bose, Jude A Rivers
Proc. 1st Workshop on the System Effects of Logic Soft Errors (SELSE), 2005


SoftArch: an architecture-level tool for modeling and analyzing soft errors
Xiaodong Li, Sarita V Adve, Pradip Bose, Jude A Rivers
Dependable Systems and Networks, 2005. DSN 2005. Proceedings. International Conference on, pp. 496--505

The case for microarchitectural awareness of lifetime reliability
Jayanth Srinivasan, Sarita V Adve, Pradip Bose, Jude Rivers, Y Li, D Brooks, Z Hu, K Skadron, V Srinivasan, M Gschwind, others
IEEE Micro 25(3), 70--80, 2005

Stretching the limits of clock-gating efficiency in server-class processors
H Jacobson, P Bose, Z Hu, A Buyuktosunoglu, V Zyuban, R Eickemeyer, L Eisen, J Griswell, D Logan, B Sinharoy, others
2005 - computer.org, Published by the IEEE Computer Society

Exploiting structural duplication for lifetime reliability enhancement
J Srinivasan, S V Adve, P Bose, J A Rivers
ACM SIGARCH Computer Architecture News 33(2), 520--531, ACM, 2005

Lifetime reliability: Toward an architectural solution
J Srinivasan, S V Adve, P Bose, J A Rivers
IEEE Micro 25(3), 70--80, 2005


2004

New challenges and burning issues
Pradip Bose
IEEE Micro 24(1), 5--5, IEEE Computer Society, 2004

Communication versus computation
Pradip Bose
IEEE Micro 24(5), 5--5, IEEE Computer Society, 2004

EIC's Message: General-purpose versus application-specific processors
Pradip Bose
IEEE Micro 24(3), 5--5, IEEE Computer Society, 2004


Microarchitectural techniques for power gating of execution units
Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, Pradip Bose
Proceedings of the 2004 international symposium on Low power electronics and design, pp. 32--37

EIC's Message: Chip-level microarchitecture trends
Pradip Bose
IEEE Micro 24(2), 5--5, IEEE Computer Society, 2004

Power-performance simulation: design and validation strategies
David Brooks, Pradip Bose, Margaret Martonosi
ACM SIGMETRICS Performance Evaluation Review 31(4), 13--18, ACM, 2004

The impact of technology scaling on lifetime reliability
Jayanth Srinivasan, Sarita V Adve, Pradip Bose, Jude A Rivers
Dependable Systems and Networks, 2004 International Conference on, pp. 177--186

Integrated analysis of power and performance for pipelined microprocessors
P. Bose, D. Brooks, P. Emma, M. Gschwind, V. Srinivasan, P. Strenski, V. Zyuban
IEEE Transactions on Computers 53(8), 1004--1016, IEEE, 2004

Understanding the energy efficiency of simultaneous multithreading
Y Li, D Brooks, Z Hu, K Skadron, P Bose
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, pp. 44--49

The case for lifetime reliability-aware microprocessors
J Srinivasan, S V Adve, P Bose, J A Rivers
2004 - computer.org, Published by the IEEE Computer Society

The Impact of Technology Scaling on Lifetime Reliability (PDF)
J Srinivasan, S V Adve, P Bose, J A Rivers
2004 - computer.org, Published by the IEEE Computer Society


2003

Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences
Charles Moore, Kevin W Rudd, Ruby B Lee, Pradip Bose
IEEE Micro 23(6), 8--10, IEEE Computer Society, 2003

EIC's Message: Adapting old paradigms to meet new challenges
Pradip Bose
IEEE MICRO 23(4), 0005, IEEE Computer Society, 2003

Energy efficient co-adaptive instruction fetch and issue
Alper Buyuktosunoglu, Tejas Karkhanis, David H Albonesi, Pradip Bose
Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on, pp. 147--156

Guest editors' introduction: Power and complexity aware design
Pradip Bose, David H Albonesi, Diana Marculescu
IEEE Micro 23(5), 8--11, IEEE Computer Society, 2003

Microarchitecture-level power-performance analysis: the powertimer approach
David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, P Emma, M Rosenfield
IBM J. Research and Development 47(5/6), 653--670, 2003

Early-stage definition of LPX: A low power issue-execute processor
P Bose, D Brooks, A Buyuktosunoglu, P Cook, K Das, P Emma, M Gschwind, H Jacobson, T Karkhanis, P Kudva
Power-Aware Computer Systems, pp. 89--92, Springer, 2003

Dynamically tuning processor resources with adaptive processing
D H Albonesi, R Balasubramonian, SG Dropsbo, S Dwarkadas, FG Friedman, M C Huang, V Kursun, G Magklis, M L Scott, G Semeraro, others
Computer 36(12), 49--58, 2003

Ramp: A model for reliability aware microprocessor design
J Srinivasan, S V Adve, P Bose, J Rivers, C K Hu
IBM Research Report, Citeseer, 2003

New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors
David Brooks, Pradip Bose, Viji Srinivasan, MK Gschwind, Philip G Emma, Michael G Rosenfield
IBM Journal of Research and Development 47(5.6), 653--670, IBM, 2003


2002

Optimizing pipelines for power and performance
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, Philip G Emma
Microarchitecture, 2002.(MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on, pp. 333--344

Power-efficient issue queue design
A Buyuktosunoglu, D H Albonesi, S Schuster, D Brooks, P Bose, P Cook
Power aware computing, pp. 58, 2002

Saving energy with just in time instruction delivery
T Karkhanis, J E Smith, P Bose
Proceedings of the 2002 international symposium on Low power electronics and design, pp. 178--183

Tradeoffs in power-efficient issue queue design
A Buyuktosunoglu, D H Albonesi, P Bose, P W Cook, S E Schuster
Proceedings of the 2002 international symposium on Low power electronics and design, pp. 184--189

Synchronous interlocked pipelines
H M Jacobson, P N Kudva, P Bose, P W Cook, S E Schuster
2002 - computer.org, IEEE Computer Society


2001

Ensuring dependable processor performance: an experience report on pre-silicon performance validation
Pradip Bose
Dependable Systems and Networks, 2001. DSN 2001. International Conference on, pp. 481--486

Modeling and analyzing CPU power and performance: Metrics, methods, and abstractions
M Martonosi, D Brooks, P Bose
SIGMETRICS 2001/Performance 2001-Tutorials, Citeseer

A circuit level implementation of an adaptive issue queue for power-aware microprocessors
A Buyuktosunoglu, D Albonesi, S Schuster, D Brooks, P Bose, P Cook
Proceedings of the 11th Great Lakes symposium on VLSI, pp. 73--78, 2001

Power-performance modeling and tradeoff analysis for a high end microprocessor
D Brooks, M Martonosi, J D Wellman, P Bose
Power-Aware Computer Systems, 126--136, Springer, 2001

Adaptive issue queue for reduced power at high performance
A Buyuktosunoglu, S E Schuster, D M Brooks, P Bose, P W Cook, D H Albonesi
US Patent App. 09/ ..., 2001 - Google Patents, Google Patents
US Patent App. 09/971,186


2000



Research Center." Power-Aware Microarchitecture: Modeling Challenges for Next-Generation Microprocessors
David M Brooks, Pradip Bose, Stanley E Schuster, Hans Jacobson, Prabhakar N Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta, Peter W Cook IBM TJ Watson
IEEE Micro 20(6), 2000

Turandot: a wide-issue superscalar processor model for microarchitecture exploration
M Moudgill, J Moreno, JH Moreno, JD Wellman, P Bose, L Trevillyan, John David Wellman
VLSI Design, 58--63, 2000

Performance and functional verification of microprocessors
P Bose, J A Abraham
VLSI Design, 2000, pp. 58--63

Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
D M Brooks, P Bose, S E Schuster, H Jacobson, P N Kudva, A Buyuktosunoglu, J Wellman, V Zyuban, M Gupta, P W Cook
Micro, IEEE 20(6), 26--44, IEEE, 2000


1999

Bounds modelling and compiler optimizations for superscalar performance tuning
Pradip Bose, Sunil Kim, Francis P O'Connell, William A Ciarfella
Journal of systems architecture 45(12), 1111--1137, Elsevier, 1999

Guest editors' introduction: Challenges in processor modeling and validation
Pradip Bose, Thomas M Conte, Todd M Austin
IEEE Micro pp. 3, 9--14, IEEE, 1999

Performance evaluation and validation of microprocessors
P Bose
Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pp. 226--227

Challenges in processor modeling and validation
P Bose, T M Conte, T M Austin
IEEE Micro 19(3), 9--14, 1999

Validation of Turandot, a fast processor model for microarchitecture exploration
M Moudgill, P Bose, J H Moreno
Performance, Computing and Communications Conference, 1999, pp. 451--457



1998

Bounds-based loop performance analysis: application to validation and tuning
Pradip Bose, Sunil Kim, FP O'Connel, William A Ciarfella
Performance, Computing and Communications, 1998. IPCCC'98., IEEE International, pp. 178--184

3.3 Performance Test Case Generation for Microprocessors
Pradip Bose
2013 IEEE 31st VLSI Test Symposium (VTS), pp. 54--54, 1998

Method and system for reducing average branch resolution time and effective misprediction penalty in a processor
P Bose, K S Chan, H Q Le, R E Wasmuth
US Patent 5,805,876, 1998 - Google Patents, Google Patents
US Patent 5,805,876

Performance test case generation for microprocessors
P Bose
VLSI Test Symposium, 1998, pp. 54--59

Performance analysis and its impact on design
P Bose, T M Conte
Computer 31(5), 41--49, 1998


1997

PARSIM: A parallel trace-driven simulation facility for fast and accurate performance analysis studies
A-T Nguyen, John-David Wellman, Pradip Bose
Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International, pp. 291--297

Accuracy and speed-up of parallel trace-driven architectural simulation
A-T Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini Nanda, Maged Michael
Parallel Processing Symposium, 1997. Proceedings., 11th International, pp. 39--44

Accuracy and speedup of parallel trace-driven architectural simulation
A T Nguyen, P Bose, K Ekanadham, A Nanda, M Michael
ipps, pp. 39, 1997

Trace-driven performance exploration of a PowerPC 601 OLTP workload on wide superscalar processors
J H Moreno, M Moudgill, J D Wellman, P Bose, L Trevillyan
1997 - research.ibm.com, IBM TJ Watson Research Center


1995

Use of architectural simulation tools in education
Pradip Bose
Proceedings of the 1995 workshop on Computer architecture education, pp. 7

Performance analysis and verification of super scalar processors
Pradip Bose
1995 - IBM TJ Watson Research Center, IBM TJ Watson Research Center

Architectural timing verification of CMOS RISC processors
Pradip Bose, S Surya
IBM Journal of Research and Development 39(1.2), 113--129, IBM, 1995


1994

Architectural performance verification: PowerPC processors
S Surya, Pradip Bose, Jacob A Abraham
Computer Design: VLSI in Computers and Processors, 1994. ICCD'94. Proceedings., IEEE International Conference on, pp. 344--347


1993

MHPS-Driven Early Design and Analysis of VLSI CPU Chips
Pradip Bose, J Wellman
VLSI Design, 1993. Proceedings. The Sixth International Conference on, pp. 256--259

Time attributed dependence graph scheme for prediction of execution time for a block of assignment statements with looping
P Bose
IBM Tech. Disclosure Bull36, 621--622, 1993


1992

Workload-driven floorplanning for MIPS optimization
Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim
Computer Design: VLSI in Computers and Processors, 1992. ICCD'92. Proceedings, IEEE 1992 International Conference on, pp. 387--391


1991

Early performance estimation of super scalar machine models
Pradip Bose
Computer Design: VLSI in Computers and Processors, 1991. ICCD'91. Proceedings, 1991 IEEE International Conference on, pp. 388--392


1988


Heuristic, rule-based program transformations for enhanced vectorization
Pradip Bose
1988 - IBM Thomas J. Watson Research ..., IBM Thomas J. Watson Research Division

Interactive program improvement via EAVE: an expert adviser for vectorization
P Bose
Proceedings of the 2nd international conference on Supercomputing, pp. 130, 1988


1987

DEPLOMAT: a design expert for PLA optimization, maintenance and test
Pradip Bose
1987 - IBM Thomas J. Watson Research ..., IBM Thomas J. Watson Research Division

Fast fault simulation and test generation for PLAs in a parallel processing environment
Pradip Bose
1987 - IBM Thomas J. Watson Research ..., IBM Thomas J. Watson Research Division

A brief status report on EAVE: an expert adviser for vectorization
Pradip Bose
1987 - IBM TJ Watson Research Center, IBM TJ Watson Research Center


1986

Optimal Code Generation Algorithms for Arithmetic Expressions Executing on Pipelined, Decoupled Architectures
Pradip Bose
Proceedings for the IEEE International Conference on Computer Design, pp. 43--46, 1986

Optimal code generation for expressions on super scalar machines
Pradip Bose
Proceedings of 1986 ACM Fall joint computer conference, pp. 372--379


1985

Logical fault analysis and design for testability of programmable logic arrays
PRADIP Bose
Proc. 23rd Annu. Allerton Conf, pp. 158--167, 1985


1984

Design of instruction set architectures for support of high-level languages
Pradip Bose, Edward S Davidson
ACM SIGARCH Computer Architecture News 12(3), 198--206, ACM, 1984


Year Unknown

Complexity-Effective Design
Pradip Bose, David H Albonesi, Diana Marculescu
ece.rochester.edu, 0

A Case for Energy-Aware Accounting in Large-Scale Computing Facilities
Cost Metrics, V\ictor Jim\'enez, Francisco J Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero
..., E Kursun, C Isci, A Buyuktosunoglu, P Bose..., 0

of CMOS RISC processors
P Bose, S Suva
P Bose, S Suva, 0

Architecture and Algorithms Track
Jim Bondi, Pradip Bose, Yao-Jen Chang, Bob Colwell
computer.org, 0

Welcome to ICCD 2012!
Sofi\`ene Tahar, Greg Byrd, Klaus Schneider, Pradip Bose
es.cs.uni-kl.de, 0

VSR Sort: A Novel Vectorised Sorting Algorithm and Architecture Extensions for Future
Victor Jimenez, Alper Buyuktosunoglu, Pradip Bose, Supercomputing Center, Mateo Valero, Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip B Gibbons, others
ieeexplore.ieee.org, 0

ISPASS 2009 people
Todd Austin, Dean Tullsen, Lieven Eeckhout, David Brooks, Elmoustapha Ould-Ahmed-Vall, Nadeem Malik, Byeong Kil Lee, Michiel Ronsse, Jun Yang, Rajeev Balasubramonian, others
ieeexplore.ieee.org, 0

ISPASS 2007 People
David Albonesi, Nadeem Malik, Byeong Kil Lee, David Brooks, Jose Nelson Amaral, Cristiana Amza, Rajeev Balasubramonian, Leslie Barnes, Paolo Faraboschi, Erik Hagersten, others
computer.org, 0

IBM Blue Gene/Q
PW Coteus, SA Hall, T Takken, RA Rand, S Tian, GV Kopcsay, R Bickford, FP Giordano, CM Marroquin, MJ Jeanson, others
ieeexplore.ieee.org, 0

Early Stage Microarchitectural Design for Lifetime Reliability
Jayanth Srinivasan, Sarita V Adve, Pradip Bose, Jude Rivers
Submitted for publication, 0

Gedanken experiments with Fortran do loops on the 3090 VF
P Bose
Technical Report, IBM Research Report (under clearance for publication), 0

The MET: A Microarchitecture Exploration Toolset
J Moreno, M Moudgill, JD Wellman, P Bose
Technical Report, Research Report (in preparation), IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 0

Turandot: A PowerPC-based wide-issue superscalar processor model for microarchitecture exploration
M Moudgill, J Moreno, P Bose, JD Wellman
Technical Report, Research Report (in preparation), IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 0