Pradip Bose 
contact information
Distinguished RSM & Manager - Efficient & Resilient SystemsThomas J. Watson Research Center, Yorktown Heights, NY USA +1
9149453478
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Professional Associations
Professional Associations: ACM | ACM SIGARCH | ACM SIGMICRO | IEEE | IEEE Computer Society2015
EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,077,170
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,077,170
ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,082,070
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,082,070
ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,082,069
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,082,069
PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,081,123
Pradip Bose, Alper Buyuktosunoglu, Hans Jacobson, Victor Zyuban
US Patent 20,150,081,123
2014
Virtualized abstraction with built-in data alignment and simultaneous event monitoring in performance counter based application characterization and tuning
Pradip Bose, Alper Buyuktosunoglu, Canturk Isci, Jeff Kephart, Xiaoqiao Meng, Ruhi Sarikaya
US Patent 8,798,962
Pradip Bose, Alper Buyuktosunoglu, Canturk Isci, Jeff Kephart, Xiaoqiao Meng, Ruhi Sarikaya
US Patent 8,798,962
Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits
Pradip Bose, Alper Buyuktosunoglu, John A Darringer, Moinuddin K Qureshi, Jeonghee Shin
US Patent 8,683,418
Pradip Bose, Alper Buyuktosunoglu, John A Darringer, Moinuddin K Qureshi, Jeonghee Shin
US Patent 8,683,418
Method and system for controlling power in a chip through a power performance monitor and control unit
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Prabhakar N Kudva
US Patent 8,639,955
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Prabhakar N Kudva
US Patent 8,639,955
2013
Power management for a computer system
Pradip Bose, Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/837,655
Pradip Bose, Bruce M Fleischer, Thomas W Fox, Hans M Jacobson, Ravi Nair
US Patent App. 13/837,655
Guarded, multi-metric resource control for safe and efficient microprocessor management
Pradip Bose, Alper Buyuktosunoglu, Niti Madan
US Patent 8,527,994
Pradip Bose, Alper Buyuktosunoglu, Niti Madan
US Patent 8,527,994
Measuring data switching activity in a microprocessor
Pradip Bose, Alper Buyuktosunoglu, Christopher J Gonzalez, Moinuddin K Qureshi, Victor Zyuban
US Patent 8,458,501
Pradip Bose, Alper Buyuktosunoglu, Christopher J Gonzalez, Moinuddin K Qureshi, Victor Zyuban
US Patent 8,458,501
Processor with memory-embedded pipeline for table-driven computation
Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C Hunter, Jude A Rivers, Vijayalakshmi Srinivasan
US Patent App. 14/053,978
Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C Hunter, Jude A Rivers, Vijayalakshmi Srinivasan
US Patent App. 14/053,978
Voltage regulator module with power gating and bypass
Pradip Bose, Alper Buyuktosunoglu, Hans M Jacobson, Seongwon Kim
US Patent 8,564,262
Pradip Bose, Alper Buyuktosunoglu, Hans M Jacobson, Seongwon Kim
US Patent 8,564,262
2012
Managing instructions for more efficient load/store unit usage
Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, Dung Quoc Nguyen, Bruce Joseph Ronchetti
US Patent 8,271,765
Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, Dung Quoc Nguyen, Bruce Joseph Ronchetti
US Patent 8,271,765
Dynamic power distribution
Pradip Bose, Alper Buyuktosunoglu, Hans M Jacobson
US Patent App. 13/685,912
Pradip Bose, Alper Buyuktosunoglu, Hans M Jacobson
US Patent App. 13/685,912
Thread consolidation in processor cores
Pradip Bose, Alper Buyuktosunoglu, Bryan S Rosenburg, Kyung D Ryu, Augusto J Vega
US Patent App. 13/681,497
Pradip Bose, Alper Buyuktosunoglu, Bryan S Rosenburg, Kyung D Ryu, Augusto J Vega
US Patent App. 13/681,497
Power Shifting in Multicore Platforms by Varying SMT Levels
Pradip Bose, Alper Buyuktosunoglu, Dilma Menezes Da Silva, Hubertus Franke, Priyanka Tembey
US Patent App. 13/476,179
Pradip Bose, Alper Buyuktosunoglu, Dilma Menezes Da Silva, Hubertus Franke, Priyanka Tembey
US Patent App. 13/476,179
Method and system for soft error recovery during processor execution
Pradip Bose, Jude A Rivers, Victor Zyuban
US Patent 8,108,714
Pradip Bose, Jude A Rivers, Victor Zyuban
US Patent 8,108,714
Modeling system-level effects of soft errors
Pradip Bose, Prabhakar N Kudva, Jude A Rivers, Pia N Sanda, John-David Wellman
US Patent 8,091,050
Pradip Bose, Prabhakar N Kudva, Jude A Rivers, Pia N Sanda, John-David Wellman
US Patent 8,091,050
Two-level guarded predictive power gating
Jayanta Basak, Pradip Bose, Alper Buyuktosunoglu, Anita Lungu
US Patent 8,219,833
Jayanta Basak, Pradip Bose, Alper Buyuktosunoglu, Anita Lungu
US Patent 8,219,833
Predictive power gating with optional guard mechanism
Jayanta Basak, Pradip Bose, Alper Buyuktosunoglu, Anita Lungu
US Patent 8,219,834
Jayanta Basak, Pradip Bose, Alper Buyuktosunoglu, Anita Lungu
US Patent 8,219,834
Adaptive data prefetch
Pradip Bose, Alper Buyuktosunoglu, Miles Robert Dooley, Michael Stephen Floyd, David Scott Ray, Bruce Joseph Ronchetti
US Patent 8,156,287
Pradip Bose, Alper Buyuktosunoglu, Miles Robert Dooley, Michael Stephen Floyd, David Scott Ray, Bruce Joseph Ronchetti
US Patent 8,156,287
On-chip power proxy based architecture
Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd
US Patent 8,271,809
Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd
US Patent 8,271,809
Method and system for controlling power in a chip through a power-performance monitor and control unit
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Prabhakar N Kudva
US Patent 8,112,642
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Prabhakar N Kudva
US Patent 8,112,642
Systems and methods for thread assignment and core turn-off for integrated circuit energy efficiency and high-performance
Pradip Bose, Alper Buyuktosunoglu, Eren Kursun
US Patent 8,296,773
Pradip Bose, Alper Buyuktosunoglu, Eren Kursun
US Patent 8,296,773
2011
Hardware Execution Driven Application Level Derating Calculation for Soft Error Rate Analysis
Pradip Bose, Meeta S Gupta, Prabhakar N Kudva, Daniel A Prener
US Patent App. 13/271,827
Pradip Bose, Meeta S Gupta, Prabhakar N Kudva, Daniel A Prener
US Patent App. 13/271,827
Local Computation Logic Embedded in a Register File to Accelerate Programs
Pradip Bose, Alper Buyuktosunoglu, Jeffrey Haskell Derby, Michele Martino Franceschini, Robert Kevin Montoye, Augusto J Vega
US Patent App. 13/211,701
Pradip Bose, Alper Buyuktosunoglu, Jeffrey Haskell Derby, Michele Martino Franceschini, Robert Kevin Montoye, Augusto J Vega
US Patent App. 13/211,701
Write filter cache method and apparatus for protecting the microprocessor core from soft errors
Pradip Bose, Zhigang Hu, Xiaodong Li, Jude A Rivers
US Patent 7,921,331
Pradip Bose, Zhigang Hu, Xiaodong Li, Jude A Rivers
US Patent 7,921,331
Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes
Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd
US Patent 8,001,394
Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd
US Patent 8,001,394
Method and system of peak power enforcement via autonomous token-based control and management
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Zhigang Hu, Hans Jacobson, Prabhakar N Kudva, Vijayalakshmi Srinivasan, Victor Zyuban
US Patent 7,930,578
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Zhigang Hu, Hans Jacobson, Prabhakar N Kudva, Vijayalakshmi Srinivasan, Victor Zyuban
US Patent 7,930,578
2010
LOW OVERHEAD DYNAMIC THERMAL MANAGEMENT IN MANY-CORE CLUSTER ARCHITECTURE
Eren Kursun, Philip G. Emma, Pradip Bose, Jude A Rivers
US Patent App. 12/698,545
Eren Kursun, Philip G. Emma, Pradip Bose, Jude A Rivers
US Patent App. 12/698,545
2009
System and method of workload-dependent reliability projection and monitoring for microprocessor chips and systems
Pradip Bose, Jude A Rivers, Jayanth Srinivasan
US Patent 7,506,216
Pradip Bose, Jude A Rivers, Jayanth Srinivasan
US Patent 7,506,216
Method of stalling one or more stages in an interlocked synchronous pipeline
Hans M Jacobson, Prabhakar N Kudva, Pradip Bose, Peter W Cook, Stanley E Schuster
US Patent 7,475,227
Hans M Jacobson, Prabhakar N Kudva, Pradip Bose, Peter W Cook, Stanley E Schuster
US Patent 7,475,227
METHOD OF VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT AND MULTITHREADED PROCESSOR WITH VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT
Chen Yong CHER, Hendrik HAMANN, Pradip BOSE, Hubertus FRANKE, Alan WEGER, Eren KURSUN
WO Patent WO/2009/027,153
Chen Yong CHER, Hendrik HAMANN, Pradip BOSE, Hubertus FRANKE, Alan WEGER, Eren KURSUN
WO Patent WO/2009/027,153
Methods for Thermal Management of Three-dimensional Integrated Circuits
Eren Kursun, Pradip Bose, Alper Buyuktosunoglu
US Patent 7,487,012
Eren Kursun, Pradip Bose, Alper Buyuktosunoglu
US Patent 7,487,012
Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system
P Bose, A Buyuktosunoglu, C Y Cher, M K Gschwind, R Nair, R A Philhower, W Sauer, R C Yeung
US Patent 7,627,742
P Bose, A Buyuktosunoglu, C Y Cher, M K Gschwind, R Nair, R A Philhower, W Sauer, R C Yeung
US Patent 7,627,742
Method for extending lifetime reliability of digital logic devices through reversal of aging mechanisms
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent 7,486,107
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent 7,486,107
2008
Predicting microprocessor lifetime reliability using architecture-level structure-aware techniques
Pradip Bose, Zhigang Hu, Jude A Rivers, Jeonghee Shin, Victor Zyuban
US Patent App. 12/189,416
Pradip Bose, Zhigang Hu, Jude A Rivers, Jeonghee Shin, Victor Zyuban
US Patent App. 12/189,416
SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP
Eren Kursun, J udeA Rivers, Pradip Bose, Victor Zyuban
US Patent App. 12/174,198
Eren Kursun, J udeA Rivers, Pradip Bose, Victor Zyuban
US Patent App. 12/174,198
Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent 7,391,233
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent 7,391,233
Dynamic redundancy for microprocessor components and circuits placed in nonoperational modes
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent App. 11/969,436
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent App. 11/969,436
Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches
Pradip Bose, Alper Buyuktosunoglu, Richard J Eickemeyer, Lee E Eisen, Philip G Emma, John B Griswell, Zhigang Hu, Hung Q Le, Douglas R Logan, Balaram Sinharoy, others
US Patent 7,392,366
Pradip Bose, Alper Buyuktosunoglu, Richard J Eickemeyer, Lee E Eisen, Philip G Emma, John B Griswell, Zhigang Hu, Hung Q Le, Douglas R Logan, Balaram Sinharoy, others
US Patent 7,392,366
Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power
Pradip Bose, Alper Buyuktosunoglu, Zhigang Hu, Hans Mikael Jacobson, Vijayalakshmi Srinivasan, Victor Zyuban
US Patent 7,447,923
Pradip Bose, Alper Buyuktosunoglu, Zhigang Hu, Hans Mikael Jacobson, Vijayalakshmi Srinivasan, Victor Zyuban
US Patent 7,447,923
Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques
Pradip Bose, Zhigang Hu, Jude A Rivers, Jeonghee Shin, Victor Zyuban
US Patent 7,472,038
Pradip Bose, Zhigang Hu, Jude A Rivers, Jeonghee Shin, Victor Zyuban
US Patent 7,472,038
Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent 7,391,232
Pradip Bose, Jeonghee Shin, Victor Zyuban
US Patent 7,391,232
Method and apparatus for monitoring and enhancing on-chip microprocessor reliability
Pradip Bose, Jude A Rivers, Jayanth Srinivasan
US Patent 7,454,316
Pradip Bose, Jude A Rivers, Jayanth Srinivasan
US Patent 7,454,316
2007
Reliability morph for a dual-core transaction-processing system
Pradip Bose, Philip George Emma, Jude A Rivers, Sumedh Wasudeo Sathaye
US Patent App. 11/684,987
Pradip Bose, Philip George Emma, Jude A Rivers, Sumedh Wasudeo Sathaye
US Patent App. 11/684,987
Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
Pradip Bose, Tejas S Karkhanis, Srinivasan Ramani, Malcolm Scott Ware, Ken Vu
US Patent 7,249,331
Pradip Bose, Tejas S Karkhanis, Srinivasan Ramani, Malcolm Scott Ware, Ken Vu
US Patent 7,249,331
METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION
Pradip Bose, Eren Kursun, Jude A Rivers, Victor Zyuban
US Patent App. 11/948,376
Pradip Bose, Eren Kursun, Jude A Rivers, Victor Zyuban
US Patent App. 11/948,376
METHOD AND ARRANGEMENT FOR ENHANCING PROCESS VARIABILITY AND LIFETIME RELIABILITY THROUGH 3D INTEGRATION
Pradip Bose, E Kursun, Jude A Rivers, Victor Zyuban
US Patent App. 11/947,207
Pradip Bose, E Kursun, Jude A Rivers, Victor Zyuban
US Patent App. 11/947,207
2006
Processor with low overhead predictive supply voltage gating for leakage power reduction
P Bose, D M Brooks, P W Cook, P G Emma, M K Gschwind, S E Schuster, V Srinivasan
US Patent 7,134,028
P Bose, D M Brooks, P W Cook, P G Emma, M K Gschwind, S E Schuster, V Srinivasan
US Patent 7,134,028
Interlocked synchronous pipeline clock gating
Hans M Jacobson, Prabhakar N Kudva, Pradip Bose, Peter W Cook, Stanley E Schuster
US Patent 7,065,665
Hans M Jacobson, Prabhakar N Kudva, Pradip Bose, Peter W Cook, Stanley E Schuster
US Patent 7,065,665
Processor with demand-driven clock throttling power reduction
Pradip Bose, Daniel M Citron, Peter W Cook, Philip G Emma, Hans M Jacobson, Prabhakar N Kudva, Stanley E Schuster, Jude A Rivers, Victor V Zyuban
US Patent 7,076,681
Pradip Bose, Daniel M Citron, Peter W Cook, Philip G Emma, Hans M Jacobson, Prabhakar N Kudva, Stanley E Schuster, Jude A Rivers, Victor V Zyuban
US Patent 7,076,681
2005
Method and structure for short range leakage control in pipelined circuits
Hans M Jacobson, Pradip Bose, Alper Buyuktosunoglu, Peter William Cook, Philip George Emma, Prabhakar N Kudva, Stanley Everett Schuster
US Patent 6,946,869
Hans M Jacobson, Pradip Bose, Alper Buyuktosunoglu, Peter William Cook, Philip George Emma, Prabhakar N Kudva, Stanley Everett Schuster
US Patent 6,946,869
2000
Performance evaluation of processor operation using trace pre-processing
Pradip Bose
US Patent 6,059,835
Pradip Bose
US Patent 6,059,835