Pritish Narayanan

contact information

Research Staff Member
Almaden Research Center, San Jose, CA, USA
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Professional Associations

Professional Associations: IEEE Solid State Circuits Society | IEEE, Senior Member

2021

Fully on-chip MAC at 14nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format
P Narayanan, S Ambrogio, A Okazaki, K Hosokawa, H Tsai, et. al.
2021 Symposium on VLSI Technology, pp. T1-T2

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices
K Spoon, H Tsai, et. al.
Frontiers in Computational Neuroscience, 53, 2021

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited)
Kohji Hosokawa, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Andrea Fasoli, Alexander Friz, An Chen, Jose Luquin, Katherine Spoon, Geoffrey W. Burr, Scott C. Lewis
2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, IEEE
Abstract artificial neural network, domain, inference, computer engineering, reliability, phase change memory, computer science, non volatile memory, segmentation, acceleration

Noise-Resilient DNN: Tolerating Noise in PCM-Based AI Accelerators via Noise-Aware Training
S Kariyappa, H Tsai, et. al.
IEEE Transactions on Electron Devices 68(9), 4356-4362, 2021

2020

Overview of the IBM Neural Computer Architecture
Pritish Narayanan, Charles E. Cox, Alexis Asseman, Nicolas Antoine, Harald Huels, Winfried W. Wilcke, Ahmet S. Ozcan
arXiv preprint arXiv:2003.11178, 2020
Abstract simd, field programmable gate array, ibm, scalability, parallel processing, computer architecture, flexibility, computer science, topology, computational neuroscience

Enabling High-Performance DNN Inference Accelerators Using Non-Volatile Analog Memory (Invited)
An Chen, Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, Alexander Friz, Andrea Fasoli, Geoffrey W. Burr
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp. 1-4, IEEE
Abstract analog computer, phase change memory, cmos, artificial neural network, noise, inference, computer hardware, computer science, analog memory, term memory

Inference of Deep Neural Networks with Analog Memory Devices
Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, An Chen, Andrea Fasoli, Alexander Friz, Geoffrey W. Burr
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), IEEE
Abstract encoding, artificial neural network, non volatile memory, inference, electronic engineering, efficient energy use, acceleration, scheme, computer science, deep neural networks

Optimization of Analog Accelerators for Deep Neural Networks Inference
Andrea Fasoli, Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, Alexander Friz, An Chen, Geoffrey W. Burr
2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, IEEE
Abstract neuromorphic engineering, von neumann architecture, non volatile memory, inference, efficient energy use, computer engineering, computation, computer science, software, acceleration

Analog acceleration of deep learning using phase-change memory
Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Robert M. Shelby, Geoffrey W. Burr
Woodhead Publishing, 2020
Abstract phase change memory, non volatile memory, deep learning, mnist database, computer engineering, field, computer science, key, acceleration, face, artificial intelligence

Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges
Charles Mackin, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Katie Spoon, Andrea Fasoli, An Chen, Alexander Friz, Robert M. Shelby, Geoffrey W. Burr
2020 IEEE International Reliability Physics Symposium (IRPS), pp. 1-10, IEEE
Abstract neuromorphic engineering, artificial neural network, phase change memory, reliability, electronic engineering, acceleration, computer science, analog memory, deep neural networks, phase change

Accelerating Deep Neural Networks with Analog Memory Devices
Katie Spoon, Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, An Chen, Andrea Fasoli, Alexander Friz, Geoffrey W. Burr
2020 IEEE International Memory Workshop (IMW), pp. 1-4, IEEE
Abstract deep learning, artificial neural network, phase change memory, speedup, electronic engineering, computation, computer science, focus, inference, artificial intelligence, deep neural networks

2019

Analog memory-based techniques for accelerating the training of fully-connected deep neural networks (Conference Presentation)
Hsinyu Tsai, Stefano Ambrogio, Pritish Narayanan, Robert M. Shelby, Charles Mackin, Geoffrey W. Burr
Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 201910958, SPIE
Abstract deep learning, artificial neural network, conventional memory, neuromorphic engineering, synaptic weight, non volatile memory, mnist database, backpropagation, computer engineering, artificial intelligence

Crossbar arrays of resistive non-volatile memories (NVMs) offer a novel and innovative solution for deep learning tasks which are typically implemented on GPUs [1]. The highly parallel structure employed in these architectures enables fast and energy-efficient multiply-accumulate computations, which is the workhorse of most deep learning algorithms. More specifically, we are developing analog hardware platforms for acceleration of large Fully Connected (FC) Deep Neural Networks (DNNs) [1,2], where training is performed using the backpropagation algorithm. This algorithm is a supervised form of learning based on three steps: forward propagation of input data through the network (a.k.a. forward inference), comparison of the inference results with ground truth labels and backpropagation of the errors from the output to the input layer, and then in-situ weight updates. This type of supervised training has been shown to succeed even in the presence of a substantial number of faulty NVMs, relaxing yield requirements vis-a-vis conventional memory, where near 100% yield may be required [2]. We recently surveyed the use of analog memory devices for DNN hardware accelerators based on crossbar array structures and discussed design choices, device and circuit readiness, and the most promising opportunities compared digital accelerators [3].In this presentation, we will focus on our implementation of an analog memory cell based on Phase-Change Memory (PCM) and 3-Transistor 1-Capacitor (3T1C) [4]. Software-equivalent accuracy on various datasets (MNIST, MNIST with noise, CIFAR-10, CIFAR-100) was achieved in a mixed software-hardware demonstration with DNN weights stored in real PCM device arrays as analog conductances. We will discuss how limitations from real-world non-volatile memory (NVM), such as conductance linearity and variability affects DNN training and how using two pairs of analog weights with varying significance relaxes device requirements [5, 6, 7]. Finally, we summarize all pieces needed to build an analog accelerator chip [8] and how lithography plays a role in future development of novel NVM devices.References:[1] G. W. Burr et al., "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element" IEDM Tech. Digest, 29.5 (2014). [2] G. W. Burr et al., "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses) using phase-change memory as the synaptic weight element", IEEE Trans. Elec. Dev, 62(11), pp. 3498 (2015).[3] H. Tsai et al., "Recent progress in analog memory-based accelerators for deep learning", Journal of Physics D: Applied Physics, 51 (28), 283001 (2018)[4] S. Ambrogio et al., "Equivalent-Accuracy Accelerated Neural Network Training using Analog Memory", Nature, 558 (7708), 60 (2018).[5] T. Gokmen et al., "Acceleration of deep neural network training with resistive cross-point devices: design considerations", Frontiers in neuroscience, 10, 333 (2016).[6] S. Sidler et al., "Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: impact of conductance response", ESSDERC Proc., 440 (2016).[7] G. Cristiano et al., "Perspective on Training Fully Connected Networks with Resistive Memories: Device Requirements for Multiple Conductances of Varying Significance", accepted in Journal of Applied Physics (2018).[8] P. Narayanan et al., "Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory", IBM J. Res. Dev., 61 (4), 1-11 (2017).

Neuro-Inspired Computing: From Resistive Memory to Optics
Charles Mackin, Pritish Narayanan, Hsinyu Tsai, Stefano Ambrogio, An Chen, Geoffrey W. Burr
2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC), pp. 1-1, IEEE
Abstract von neumann architecture, speedup, bottleneck, throughput, parallel computing, efficient energy use, resistive random access memory, computer science, inference, deep neural networks

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems
Alessandro Fumarola, Y. Leblebici, P. Narayanan, R.M. Shelby, L.L. Sanchez, G.W. Burr, K. Moon, J. Jang, H. Hwang, S. Sidler
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), pp. 1-6, IEEE
Abstract neuromorphic engineering, artificial neural network, non volatile memory, crossbar switch, mnist database, multiplication, backpropagation, computational science, path, computer science

Training fully connected networks with resistive memories: impact of device failures
Louis P. Romero, Stefano Ambrogio, Massimo Giordano, Massimo Giordano, Giorgio Cristiano, Giorgio Cristiano, Martina Bodini, Martina Bodini, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Geoffrey W. Burr
Faraday Discussions213, 371-391, The Royal Society of Chemistry, 2019
Abstract neuromorphic engineering, crossbar switch, robustness, electrical element, computer engineering, cmos, resistive touchscreen, computer science, deep neural networks, hidden layer

Weight programming in DNN analog hardware accelerators in the presence of NVM variability
C Mackin, H Tsai, et. al.
Advanced Electronic Materials 5(9), 1900026, 2019

Reducing the impact of phase-change memory conductance drift on the inference of large-scale hardware neural networks
S Ambrogio, M Gallot, K Spoon, H Tsai, et. al.
2019 IEEE International Electron Devices Meeting (IEDM), pp. 6.1.1-6.1.4

2018

Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?"
Koji Inoue, Takuya Araki, Takumi Maruyama, Pritish Narayanan, Takashi Oshima, Martin Schulz
2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-2, IEEE
Abstract green computing, system on a chip, software, information and communications technology, industrial engineering, computer science, dram, chip, scaling, sustainable power

Hierarchical temporal memory system
Geoffrey Burr, Pritish Narayanan
2018
Abstract hierarchical temporal memory, component, sequence, pattern recognition, computer science, artificial intelligence, distributed representation

Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part I: Al/Mo/Pr 0.7 Ca 0.3 MnO 3 Material Improvements and Device Measurements
Kibong Moon, Alessandro Fumarola, Severin Sidler, Junwoo Jang, Pritish Narayanan, Robert M. Shelby, Geoffrey W. Burr, Hyunsang Hwang
IEEE Journal of the Electron Devices Society 6(1), 146-155, IEEE, 2018
Abstract synapse part, resistive random access memory, electrode, neuromorphic engineering, conductance, activation energy, optoelectronics, voltage, materials science, layer

Perspective on training fully connected networks with resistive memories: Device requirements for multiple conductances of varying significance
Giorgio Cristiano, Giorgio Cristiano, Massimo Giordano, Massimo Giordano, Stefano Ambrogio, Louis P. Romero, Christina Cheng, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Geoffrey W. Burr
Journal of Applied Physics 124(15), AIP Publishing LLC AIP Publishing, 2018
Abstract encoding, conductance, crossbar switch, resistive touchscreen, artificial neural network, energy, open loop controller, dynamic range, topology, computer science

Novel Deep Neural Network (DNN) accelerators based on crossbar arrays of non-volatile memories (NVMs)such as Phase-Change Memory or Resistive Memorycan implement multiply-accumulate operations in a highly parallelized fashion. In such systems, computation occurs in the analog domain at the location of weight data encoded into the conductances of the NVM devices. This allows DNN training of fully-connected layers to be performed faster and with less energy. Using a mixed-hardware-software experiment, we recently showed that by encoding each weight into four distinct physical devicesa "Most Significant Conductance" pair (MSP) and a "Least Significant Conductance" pair (LSP)we can train DNNs to software-equivalent accuracy despite the imperfections of real analog memory devices. We surmised that, by dividing the task of updating and maintaining weight values between the two conductance pairs, this approach should significantly relax the otherwise quite stringent device requirements. In this paper, we quantify these relaxed requirements for analog memory devices exhibiting a saturating conductance response, assuming either an immediate or a delayed steep initial slope in conductance change. We discuss requirements on the LSP imposed by the "Open Loop Tuning" performed after each training example and on the MSP due to the "Closed Loop Tuning" performed periodically for weight transfer between the conductance pairs. Using simulations to evaluate the final generalization accuracy of a trained four-neuron-layer fully-connected network, we quantify the required dynamic range (as controlled by the size of the steep initial jump), the tolerable device-to-device variability in both maximum conductance and maximum conductance change, the tolerable pulse-to-pulse variability in conductance change, and the tolerable device yield, for both the LSP and MSP devices. We also investigate various Closed Loop Tuning strategies and describe the impact of the MSP/LSP approach on device endurance.

Recent progress in analog memory-based accelerators for deep learning
H Tsai, et. al.
Journal of Physics D: Applied Physics 51(28), 283001, 2018

Equivalent-accuracy accelerated neural-network training using analogue memory
Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Irem Boybat, Carmelo di Nolfo, Severin Sidler, Massimo Giordano, Martina Bodini, Nathan C. P. Farinha, Benjamin Killeen, Christina Cheng, Yassine Jaoudi, Geoffrey W. Burr
Nature 558(7708), 60--67, 2018
Abstract

2017

Nonvolatile Memory Crossbar Arrays for Non-von Neumann Computing
Sidler, Severin and Jang, Jun-Woo and Burr, Geoffrey W and Shelby, Robert M and Boybat, Irem and Di Nolfo, Carmelo and Narayanan, Pritish and Virwani, Kumar and Hwang, Hyunsang
Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices, pp. 129--149, Springer, 2017
Abstract

Multilayer Perceptron Algorithm: Impact of Nonideal Conductance and Area-Efficient Peripheral Circuits
L. L. Sanches, A. Fumarola, S. Sidler, P. Narayanan, I. Boybat, J. Jang, K. Moon, R. M. Shelby, Y. Leblebici, H. Hwang and G. W. Burr
Neuro-inspired Computing Using Resistive Synaptic Devices, 2017

Neuromorphic devices and architectures for next-generation cognitive computing
Geoffrey W. Burr, Pritish Narayanan, Robert M. Shelby, Stefano Ambrogio, Hsinyu Tsai, Scott L. Lewis, Kohji Hosokawa
2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, IEEE
Abstract neuromorphic engineering, cognitive computing, synaptic weight, backpropagation, computer architecture, system on a chip, parallel computing, computer science, focus, non volatile memory

Neuromorphic technologies for next-generation cognitive computing
Shelby, Robert M and Narayanan, Pritish and Ambrogio, Stefano and Tsai, Hsinyu and Hosokawa, Kohji and Lewis, Scott C and Burr, Geoffrey W
Electron Devices Technology and Manufacturing Conference (EDTM), 2017 IEEE, pp. 8--9
Abstract

Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays
Pritish Narayanan, Lucas L. Sanches, Alessandro Fumarola, Robert M. Shelby, Stefano Ambrogio, Junwoo Jang, Hyunsang Hwang, Yusuf Leblebici, Geoffrey W. Burr
2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, IEEE
Abstract circuit design, neuromorphic engineering, massively parallel, speedup, non volatile memory, electronic circuit, reset, computer science, machine learning, neuron, artificial intelligence

Neuromorphic computing using non-volatile memory
Geoffrey W Burr, Robert M Shelby, Abu Sebastian, Sangbum K im, Seyoung Kim, Severin Sidler, Kumar Virwani, Masatoshi Ishii, Pritish Narayanan, Alessandro Fumarola, others
Advances in Physics: X 2(1), 89--124, Taylor \& Francis, 2017

2016

Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs
Alessandro Fumarola, Pritish Narayanan, Lucas L. Sanches, Severin Sidler, Junwoo Jang, Kibong Moon, Robert M. Shelby, Hyunsang Hwang, Geoffrey W. Burr
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, Ieee
Abstract semiconductor memory, non volatile random access memory, memory refresh, non volatile memory, interleaved memory, sense amplifier, registered memory, flat memory model, computer hardware, computer science

Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Impact of conductance response
S. Sidler, I. Boybat, R. M. Shelby, P. Narayanan, J. Jang, A. Fumarola, K. Moon, Y. Leblebici, H. Hwang, and G. W. Burr
European Solid-State Device Research Conference (ESSDERC), 2016

2015

On the Origin of Steep $I$ - $V$ Nonlinearity in Mixed-Ionic-Electronic-Conduction-Based Access Devices
Alvaro Padilla, Geoffrey W. Burr, Rohit S. Shenoy, Karthik V. Raman, Donald S. Bethune, Robert M. Shelby, Charles T. Rettner, Juned Mohammad, Kumar Virwani, Pritish Narayanan, Arpan K. Deb, Rajan K. Pandey, Mohit Bajaj, K. V. R. M. Murali, Bulent N. Kurdi, Kailash Gopalakrishnan
IEEE Transactions on Electron Devices 62(3), 963-971, 2015
Abstract thermal conduction, semiconductor device modeling, semiconductor, physics, leakage, ion, hall effect, electronic engineering, electrode, band gap

Exploring the Design Space for Crossbar Arrays Built With Mixed-Ionic-Electronic-Conduction (MIEC) Access Devices
Pritish Narayanan, Geoffrey W. Burr, Rohit S. Shenoy, Samantha Stephens, Kumar Virwani, Alvaro Padilla, Bulent N. Kurdi, Kailash Gopalakrishnan
IEEE Journal of the Electron Devices Society 3(5), 423-434, IEEE, 2015
Abstract non volatile memory, crossbar switch, leakage, voltage, subthreshold slope, spice, equivalent series resistance, electrical engineering, electronic engineering, stacking, engineering

Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power)
G. W. Burr, P. Narayanan, R. M. Shelby, S. Sidler, I. Boybat, C. di Nolfo, Y. Leblebici
2015 IEEE International Electron Devices Meeting (IEDM)
Abstract artificial neural network, synaptic weight, non volatile memory, system on a chip, computer engineering, power, computer science, scale, element

Experimental demonstration and tolerancing of a large-scale neural network (165 000 synapses) using phase-change memory as the synaptic weight element
Burr, Geoffrey W and Shelby, Robert M and Sidler, Severin and Di Nolfo, Carmelo and Jang, Junwoo and Boybat, Irem and Shenoy, Rohit S and Narayanan, Pritish and Virwani, Kumar and Giacometti, Emanuele U and others
IEEE Transactions on Electron Devices 62(11), 3498--3507, IEEE, 2015
Abstract

Deep learning with limited numerical precision
Gupta, Suyog and Agrawal, Ankur and Gopalakrishnan, Kailash and Narayanan, Pritish
Proceedings of the 32nd International Conference on Machine Learning (ICML-15), pp. 1737--1746, 2015
Abstract

2014

Exploring the design space for resistive nonvolatile memory crossbar arrays with mixed ionic-electronic-conduction (MIEC)-based Access Devices
P. Narayanan, G. W. Burr, R. S. Shenoy, S. Stephens, K. Virwani, A. Padilla, B. Kurdi, K. Gopalakrishnan
Device Research Conference (DRC), 2014 72nd Annual, pp. 239-240, IEEE
non volatile memory, crossbar switch, resistive touchscreen, optoelectronics, thermal conduction, electronic engineering, ionic bonding, materials science, design space

The origin of massive nonlinearity in Mixed-Ionic-Electronic-Conduction (MIEC)-based Access Devices, as revealed by numerical device simulation
A. Padilla, G. W. Burr, R. S. Shenoy, K. V. Raman, D. Bethune, R. M. Shelby, C. T. Rettner, J. Mohammad, K. Virwani, P. Narayanan, A. K. Deb, R. K. Pandey, M. Bajaj, K. V. R. M. Murali, B. N. Kurdi, K. Gopalakrishnan
Device Research Conference (DRC), 2014 72nd Annual, pp. 163-164
thermal conduction, physics, optoelectronics, numerical device simulation, nonlinear system, ionic bonding, electronic engineering

Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays
P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, B. Kurdi
2014 IEEE International Electron Devices Meeting, IEEE
Abstract non volatile memory, crossbar switch, resistive touchscreen, voltage, electronic engineering, current, benchmarking, engineering, design space

MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays
Shenoy, Rohit S and Burr, Geoffrey W and Virwani, Kumar and Jackson, Bryan and Padilla, Alvaro and Narayanan, Pritish and Rettner, Charles T and Shelby, Robert M and Bethune, Donald S and Raman, Karthik V and others
Semiconductor Science and Technology 29(10), 104005, IOP Publishing, 2014
Abstract

Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element
G.W. Burr, R.M. Shelby, C. di Nolfo, J.W. Jang, R.S. Shenoy, P. Narayanan, K. Virwani, E. Giacometti, B. Kurdi, H. Hwang
2014 IEEE International Electron Devices Meeting (IEDM) , pp. 29.5.1-29.5.4

2013

Experimental prototyping of beyond-CMOS nanowire computing fabrics
Mostafizur Rahman, Pritish Narayanan, Santosh Khasanvis, John Nicholson, Csaba Andras Moritz
2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 134-139, IEEE
Abstract beyond cmos, logic gate, cmos, application specific integrated circuit, nanowire, fabric computing, routing, transistor, electronic engineering, electrical engineering, computer science

Pritish Narayanan gen_feedback_link(leftr, rightr);