Viresh Paruthi  Viresh Paruthi photo         

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STSM Formal Verification, Member Academy of Technology
Austin TX, USA



Designer-level verification—An industrial experience story
Bergman, Stephen and Bobok, Gabor and Kowalski, Walter and Koyfman, Shlomit and Moran, Shiri and Nevo, Ziv and Orni, Avigail and Paruthi, Viresh and Roesner, Wolfgang and Shurek, Gil and others
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp. 410--411

Solutions to IBM POWER8 verification challenges
Schubert, K-D and Ludden, John M and Ayub, S and Behrend, J and Brock, B and Copty, Fady and German, SM and Hershkovitz, Oz and Horbach, H and Jackson, Jonathan R and others
IBM Journal of Research and Development 59(1), 11--1, IBM, 2015


Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry
Alexey Lvov, Luis A Lastras-Monta\~no, Barry Trager, Viresh Paruthi, Robert Shadowen, Ali El-Zein
Formal Methods in System Design, 1--24, Springer, 2014

Automatic verification of floating point units
Krautz, Udo and Paruthi, Viresh and Arunagiri, Anand and Kumar, Sujeet and Pujar, Shweta and Babinsky, Tina
Proceedings of the 51st Annual Design Automation Conference, pp. 1--6, 2014


Formal verification of error correcting circuits using computational algebraic geometry
Lvov, Alexey and Lastras-Montano, Luis A and Paruthi, Viresh and Shadowen, Robert and El-Zein, Ali
Formal Methods in Computer-Aided Design (FMCAD), 2012, pp. 141--148


Hybrid verification of a hardware modular reduction engine
Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael Case, Hari Mony
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, pp. 207--214, 2011

Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems
K.D. Schubert, W. Roesner, J.M. Ludden, J. Jackson, J. Buchert, V. Paruthi, M. Behm, A. Ziv, J. Schumann, C. Meissner, others
IBM Journal of Research and Development 55(3), 10--1, IBM, 2011


Formal Verification of Arbiters using Property Strengthening and Underapproximations
Gadiel Auerbach, Fady Copty, Viresh Paruthi
FMCAD, pp. 21-24, 2010

Large-scale application of formal verification: From fiction to fact
Paruthi, Viresh
Formal Methods in Computer-Aided Design (FMCAD), 2010, pp. 175--180


Formal verification of correctness and performance of random priority-based arbiters
Krishnan Kailas, Viresh Paruthi, Brian Monwai
Proc. of 9th International Conference on Formal Methods in Computer-Aided Design (FMCAD 2009), pp. 101-107, IEEE


Scalable sequential equivalence checking across arbitrary design transformations
H Mony, V Paruthi, R Kanzelman, G Janssen
Computer Design, 2006. ICCD 2006. International Conference …, 2007 -


Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
Paruthi, Viresh and Jacobi, Christian and Weber, Kai
Lecture notes in computer science3725, 114, Springer, 2005

Automatic formal verification of fused-multiply-add FPUs
Jacobi, Christian and Weber, Kai and Paruthi, Viresh and Baumgartner, Jason
Proceedings of the conference on Design, Automation and Test in Europe-Volume 2, pp. 1298--1303, 2005

Exploiting suspected redundancy without proving it
Mony, Hari and Baumgartner, Jason and Paruthi, Viresh and Kanzelman, Robert
Proceedings of the 42nd annual Design Automation Conference, pp. 463--466, 2005


Scalable automated verification via expert-system guided transformations
Mony, Hari and Baumgartner, Jason and Paruthi, Viresh and Kanzelman, Robert and Kuehlmann, Andreas
FMCAD, pp. 159--173, 2004


Robust Boolean reasoning for equivalence checking and functional property verification
Kuehlmann, Andreas and Paruthi, Viresh and Krohm, Florian and Ganai, Malay K
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(12), 1377--1394, IEEE, 2002

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
Ludden, John M and Roesner, Wolfgang and Heiling, Gerry M and Reysa, John R and Jackson, Jonathan R and Chu, B-L and Behm, Michael L and Baumgartner, Jason R and Peterson, Richard D and Abdulhafiz, Jamee and others
IBM Journal of Research and Development 46(1), 53--76, IBM, 2002


Circuit-based Boolean reasoning
Kuehlmann, Andreas and Ganai, Malay K and Paruthi, Viresh
Proceedings of the 38th annual Design Automation Conference, pp. 232--237, 2001


Equivalence checking combining a structural SAT-solver, BDDs, and simulation
Paruthi, Viresh and Kuehlmann, Andreas
Computer Design, 2000. Proceedings. 2000 International Conference on, pp. 459--464


Automatic data path abstraction for verification of large scale designs
Viresh Paruthi, Nazanin Mansouri and Ranga Vemuri
International Conference on Computer Design (ICCD), 1998

Year Unknown

Killer Apps: Not Your Father’s Formal Verification
Brinkmann, Raik and Hanna, Ziyad and Paruthi, Viresh and Seligman, Erik and Singhal, Vigyan, 0