John David (John David) Wellman 
contact information
ResearchThomas J. Watson Research Center, Yorktown Heights, NY USA +1
9149452523
9149452523 links
2012
Modeling system-level effects of soft errors
Pradip Bose, Prabhakar N Kudva, Jude A Rivers, Pia N Sanda, John-David Wellman
US Patent 8,091,050
Pradip Bose, Prabhakar N Kudva, Jude A Rivers, Pia N Sanda, John-David Wellman
US Patent 8,091,050
2011
Augmenting of automated clustering-based trace sampling methods by user-directed phase detection
R H Bell Jr, W T T Chen, P R Seshadri, J D Wellman, others
US Patent 8,000,953
R H Bell Jr, W T T Chen, P R Seshadri, J D Wellman, others
US Patent 8,000,953
2009
System and method of execution of register pointer instructions ahead of instruction issues
E Altman, M K Gschwind, J A Rivers, S W Sathaye, J D Wellman, V Zyuban
US Patent 7,496,733
E Altman, M K Gschwind, J A Rivers, S W Sathaye, J D Wellman, V Zyuban
US Patent 7,496,733
Non-homogeneous multi-processor system with shared memory
E.R. Altman, P.G. Capek, M.K. Gschwind, C.R. Johns, H.P. Hofstee, M.E. Hopkins, J.A. Kahle, S.W. Sathaye, J.D. Wellman, R. Nair
US Patent 7,509,457
E.R. Altman, P.G. Capek, M.K. Gschwind, C.R. Johns, H.P. Hofstee, M.E. Hopkins, J.A. Kahle, S.W. Sathaye, J.D. Wellman, R. Nair
US Patent 7,509,457
IMPLEMENTING INSTRUCTION SET ARCHITECTURES WITH NON-CONTIGUOUS REGISTER FILE SPECIFIERS
M K Gschwind, R K Montoye, B Olsson, J Wellman
US Patent App. 12/534,968
M K Gschwind, R K Montoye, B Olsson, J Wellman
US Patent App. 12/534,968
2008
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
E R Altman, M Gschwind, D A Luick, D A Prener, J A Rivers, S W Sathaye, J D Wellman
US Patent 7,340,588
E R Altman, M Gschwind, D A Luick, D A Prener, J A Rivers, S W Sathaye, J D Wellman
US Patent 7,340,588
System and method of execution of register pointer instructions ahead of instruction issue
E Altman, M K Gschwind, J A Rivers, S W Sathaye, J D Wellman, V Zyuban
US Patent 7,325,124
E Altman, M K Gschwind, J A Rivers, S W Sathaye, J D Wellman, V Zyuban
US Patent 7,325,124
Transient cache storage with discard function for disposable data
E R Altman, M K Gschwind, R K Montoye, J A Rivers, S W Sathaye, J D Wellman, V Zyuban
US Patent 7,461,209
E R Altman, M K Gschwind, R K Montoye, J A Rivers, S W Sathaye, J D Wellman, V Zyuban
US Patent 7,461,209
2007
COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION SCHEDULE CACHE
K K Kailas, R Nair, S W Sathaye, W Sauer, J Wellman
US Patent App. 20,080/162,884
K K Kailas, R Nair, S W Sathaye, W Sauer, J Wellman
US Patent App. 20,080/162,884
METHOD AND APPARATUS FOR ALLOCATING ARCHITECTURAL REGISTER RESOURCES AMONG THREADS IN A MULTI-THREADED MICROPROCESSOR CORE
A.E. Eichenberger, M.K. Gschwind, J.A. Gunnels
US Patent App. 11/869,838
A.E. Eichenberger, M.K. Gschwind, J.A. Gunnels
US Patent App. 11/869,838
SYSTEM AND STRUCTURE FOR SYNCHRONIZED THREAD PRIORITY SELECTION IN A DEEPLY PIPELINED MULTITHREADED MICROPROCESSOR
P Kudva, D S Levitan, B Sinharoy, J D Wellman
US Patent App. 11/737,491
P Kudva, D S Levitan, B Sinharoy, J D Wellman
US Patent App. 11/737,491
2006
Methods for generating code for an architecture encoding an extended register specification
M K Gschwind, R K Montoye, B Olsson, J D Wellman
US Patent App. 11/446,031
M K Gschwind, R K Montoye, B Olsson, J D Wellman
US Patent App. 11/446,031
System and method for instruction memory storage and processing based on backwards branch control information
Sameh W Asaad, Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 7,130,963
Sameh W Asaad, Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 7,130,963
2005
Method and apparatus for accessing misaligned data streams
M.K. Gschwind, J.D. Wellman
US Patent App. 11/216,659
M.K. Gschwind, J.D. Wellman
US Patent App. 11/216,659
Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors
E R Altman, P G Capek, M Gschwind, H P Hofstee, J A Kahle, R Nair, S W Sathaye, J D Wellman
US Patent 6,907,477
E R Altman, P G Capek, M Gschwind, H P Hofstee, J A Kahle, R Nair, S W Sathaye, J D Wellman
US Patent 6,907,477
Method and apparatus for control signals memoization in a multiple instruction issue microprocessor
E.R. Altman, M.K. Gschwind, J.A. Rivers, S.W. Sathaye, J.D. Wellman, V.V. Zyuban
US Patent App. 11/034,284
E.R. Altman, M.K. Gschwind, J.A. Rivers, S.W. Sathaye, J.D. Wellman, V.V. Zyuban
US Patent App. 11/034,284
2004
Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching
Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 6,711,651
Jaime H Moreno, Jude A Rivers, John-David Wellman
US Patent 6,711,651
Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
E R Altman, P G Capek, M Gschwind, H P Hofstee, J A Kahle, R Nair, S W Sathaye, J D Wellman, M Suzuoki, T Yamazaki
US Patent 6,779,049
E R Altman, P G Capek, M Gschwind, H P Hofstee, J A Kahle, R Nair, S W Sathaye, J D Wellman, M Suzuoki, T Yamazaki
US Patent 6,779,049
2000
Symmetric multi-processing system
E R Altman, P G Capek, M K Gschwind, H P Hofstee, J A Kahle, R Nair, S W Sathaye, J Wellman
US Patent App. 20,020/078,308
E R Altman, P G Capek, M K Gschwind, H P Hofstee, J A Kahle, R Nair, S W Sathaye, J Wellman
US Patent App. 20,020/078,308
Projects and Groups
Technical Areas
- AI Systems
- Algorithms and Theory
- Computational Biology
- Computer Systems Design
- Health Informatics
- Internet of Things
- Knowledge
- Knowledge Discovery and Data Mining
- Learning
- Operations Research
- Performance Modeling and Analysis
- Programming Languages & Software Engineering
- Quantum Computing
- Reasoning
- Security and Privacy
- Statistics
- Supercomputing