2015
Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches
Chudzik, Michael P and Dirahoui, Bachir and Krishnan, Rishikesh and Krishnan, Siddarth A and Kwon, Oh-Jung and Parries, Paul C and Yan, Hongwen
US Patent 9,087,927
Chudzik, Michael P and Dirahoui, Bachir and Krishnan, Rishikesh and Krishnan, Siddarth A and Kwon, Oh-Jung and Parries, Paul C and Yan, Hongwen
US Patent 9,087,927
2014
Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures
Vega, Reinaldo A and Yan, Hongwen
US Patent 8,907,405
Vega, Reinaldo A and Yan, Hongwen
US Patent 8,907,405
Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches
Chudzik, Michael P and Dirahoui, Bachir and Krishnan, Rishikesh and Krishnan, Siddarth A and Kwon, Oh-Jung and Parries, Paul C and Yan, Hongwen
US Patent 8,901,706
Chudzik, Michael P and Dirahoui, Bachir and Krishnan, Rishikesh and Krishnan, Siddarth A and Kwon, Oh-Jung and Parries, Paul C and Yan, Hongwen
US Patent 8,901,706
Array and moat isolation structures and method of manufacture
Kusaba, Naoyoshi and Kwon, Oh-Jung and Li, Zhengwen and Yan, Hongwen
US Patent 8,673,737
Kusaba, Naoyoshi and Kwon, Oh-Jung and Li, Zhengwen and Yan, Hongwen
US Patent 8,673,737
2013
Method of removing high-K dielectric layer on sidewalls of gate structure
Zhang, Ying and Yang, Qingyun and Yan, Hongwen
US Patent 8,481,389
Zhang, Ying and Yang, Qingyun and Yan, Hongwen
US Patent 8,481,389
2012
Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist
Dalton, Timothy J and Natzle, Wesley C and Pastel, Paul W and Wise, Richard S and Yan, Hongwen and Zhang, Ying
US Patent 8,198,103
Dalton, Timothy J and Natzle, Wesley C and Pastel, Paul W and Wise, Richard S and Yan, Hongwen and Zhang, Ying
US Patent 8,198,103
Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing
Khare, Mukesh V and Mo, Renee T and Ramachandran, Ravikumar and Wise, Richard S and Yan, Hongwen
US Patent 8,193,099
Khare, Mukesh V and Mo, Renee T and Ramachandran, Ravikumar and Wise, Richard S and Yan, Hongwen
US Patent 8,193,099
Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor
Coolbaugh, Douglas D and Eshun, Ebenezer E and Gebreselasie, Ephrem G and He, Zhong-Xiang and Ho, Herbert Lei and Kim, Deok-kee and Kothandaraman, Chandrasekharan and Moy, Dan and Rassel, Robert Mark and Safran, John Matthew and others
US Patent 8,159,040
Coolbaugh, Douglas D and Eshun, Ebenezer E and Gebreselasie, Ephrem G and He, Zhong-Xiang and Ho, Herbert Lei and Kim, Deok-kee and Kothandaraman, Chandrasekharan and Moy, Dan and Rassel, Robert Mark and Safran, John Matthew and others
US Patent 8,159,040
CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials
Chen, Tze-Chiang and Ieong, Meikei and Jammy, Rajarao and Khare, Mukesh V and Sung, Chun-yung and Wise, Richard and Yan, Hongwen and Zhang, Ying
US Patent 8,158,481
Chen, Tze-Chiang and Ieong, Meikei and Jammy, Rajarao and Khare, Mukesh V and Sung, Chun-yung and Wise, Richard and Yan, Hongwen and Zhang, Ying
US Patent 8,158,481
2011
Trench formation in substrate
Lee, Junedong and Li, Xi and Parries, Paul C and Wise, Richard and Yan, Hongwen
US Patent App. 13/211,570
Lee, Junedong and Li, Xi and Parries, Paul C and Wise, Richard and Yan, Hongwen
US Patent App. 13/211,570
Residue free patterned layer formation method applicable to CMOS structures
Chudzik, Michael and Doris, Bruce B and Henson, William K and Yan, Hongwen and Zhang, Ying
US Patent 7,863,124
Chudzik, Michael and Doris, Bruce B and Henson, William K and Yan, Hongwen and Zhang, Ying
US Patent 7,863,124
Direct contact between high-$kappa$/metal gate and wiring process flow
Bu, Huiming and Chudzik, Michael P and Donaton, Ricardo A and Moumen, Naim and Yan, Hongwen
US Patent 7,863,123
Bu, Huiming and Chudzik, Michael P and Donaton, Ricardo A and Moumen, Naim and Yan, Hongwen
US Patent 7,863,123
CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs
Doris, Bruce Bennett and Henson, William K and Wise, Richard Stephen and Yan, Hongwen
US Patent 8,018,005
Doris, Bruce Bennett and Henson, William K and Wise, Richard Stephen and Yan, Hongwen
US Patent 8,018,005
2010
Method of patterning multilayer metal gate structures for CMOS devices
Doris, Bruce B and Wise, Richard S and Yan, Hongwen and Zhang, Ying
US Patent 7,820,555
Doris, Bruce B and Wise, Richard S and Yan, Hongwen and Zhang, Ying
US Patent 7,820,555
Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes
Adkisson, James William and Chudzik, Michael Patrick and Gambino, Jeffrey Peter and Yan, Hongwen
US Patent 7,790,559
Adkisson, James William and Chudzik, Michael Patrick and Gambino, Jeffrey Peter and Yan, Hongwen
US Patent 7,790,559
Method of forming gate stack and structure thereof
Belyansky, Michael P and Krishnan, Siddarth A and Kwon, Unoh and Moumen, Naim and Ramachandran, Ravikumar and Schaeffer, James Kenyon and Wise, Richard and Wong, Keith Kwong Hon and Yan, Hongwen and others
US Patent 7,691,701
Belyansky, Michael P and Krishnan, Siddarth A and Kwon, Unoh and Moumen, Naim and Ramachandran, Ravikumar and Schaeffer, James Kenyon and Wise, Richard and Wong, Keith Kwong Hon and Yan, Hongwen and others
US Patent 7,691,701
Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack
Kanakasabapathy, Siva and Zhang, Ying and Sikorski, Edmund M and Yan, Hongwen and Narayanan, Vijay and Paruchuri, Vamsi K and Doris, Bruce B
US Patent 7,820,552
Kanakasabapathy, Siva and Zhang, Ying and Sikorski, Edmund M and Yan, Hongwen and Narayanan, Vijay and Paruchuri, Vamsi K and Doris, Bruce B
US Patent 7,820,552
2008
Apparatus and method for shielding a wafer from charged particles during plasma etching
Yan, Hongwen and Ji, Brian L and Panda, Siddhartha and Wise, Richard and Chen, Bomy A
US Patent 7,438,822
Yan, Hongwen and Ji, Brian L and Panda, Siddhartha and Wise, Richard and Chen, Bomy A
US Patent 7,438,822
Methods of forming high-k/metal gates for nfets and pfets
Chudzik, Michael P and Henson, William K and Moumen, Naim and Park, Dae-Gyu and Yan, Hongwen
US Patent App. 12/061,081
Chudzik, Michael P and Henson, William K and Moumen, Naim and Park, Dae-Gyu and Yan, Hongwen
US Patent App. 12/061,081
Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET
Chen, Tze-chiang and Doris, Bruce B and Jagannathan, Rangarajan and Yan, Hongwen and Yang, Qingyun and Zhang, Ying
US Patent 7,435,652
Chen, Tze-chiang and Doris, Bruce B and Jagannathan, Rangarajan and Yan, Hongwen and Yang, Qingyun and Zhang, Ying
US Patent 7,435,652
Wiring structure for integrated circuit with reduced intralevel capacitance
Wise, Richard S and Chen, Bomy A and Hakey, Mark C and Yan, Hongwen
US Patent 7,329,602
Wise, Richard S and Chen, Bomy A and Hakey, Mark C and Yan, Hongwen
US Patent 7,329,602
2007
Method and system for plasma etching having improved across-wafer etch uniformity
Yang, Qingyun and Liu, Joyce C and Yan, Hongwen and Zhang, Ying
US Patent App. 11/673,128
Yang, Qingyun and Liu, Joyce C and Yan, Hongwen and Zhang, Ying
US Patent App. 11/673,128
Methods for forming nested and isolated lines in semiconductor devices
Dobuzinsky, David M and Faltermeier, Johnathan E and Kusaba, Naoyoshi and Liu, Joyce C and Naeem, Munir D and Panda, Siddhartha and Wise, Richard S and Yan, Hongwen
US Patent App. 11/874,392
Dobuzinsky, David M and Faltermeier, Johnathan E and Kusaba, Naoyoshi and Liu, Joyce C and Naeem, Munir D and Panda, Siddhartha and Wise, Richard S and Yan, Hongwen
US Patent App. 11/874,392
Method of forming disposable spacers for improved stressed nitride film effectiveness
Liu, Joyce C and Yan, Hongwen and Yang, Qingyun and Zhang, Ying
US Patent App. 11/669,645
Liu, Joyce C and Yan, Hongwen and Yang, Qingyun and Zhang, Ying
US Patent App. 11/669,645
Gate stack structure with oxygen gettering layer
Bu, Huiming and Carter, Rick and Chudzik, Michael P and Graves, Troy L and Gribelyuk, Michael A and Jha, Rashmi and Narayanan, Vijay and Park, Dae-Gyu and Paruchuri, Vamsi K and Yan, Hongwen and others
US Patent App. 11/958,595
Bu, Huiming and Carter, Rick and Chudzik, Michael P and Graves, Troy L and Gribelyuk, Michael A and Jha, Rashmi and Narayanan, Vijay and Park, Dae-Gyu and Paruchuri, Vamsi K and Yan, Hongwen and others
US Patent App. 11/958,595
2006
Method and system for identifying bottlenecks in a securities processing system
Beacham, Michael L and Lobel, Scott M and Yan, Wendy and Ortman, Roy T
US Patent 7,127,421
Beacham, Michael L and Lobel, Scott M and Yan, Wendy and Ortman, Roy T
US Patent 7,127,421
Reduced dielectric constant spacer materials integration for high speed logic gates
Belyansky, Michael P and Liu, Joyce C and Wann, Hsing Jen and Wise, Richard Stephen and Yan, Hongwen
US Patent 7,081,393
Belyansky, Michael P and Liu, Joyce C and Wann, Hsing Jen and Wise, Richard Stephen and Yan, Hongwen
US Patent 7,081,393
Reduced dielectric constant spacer materials integration for high speed logic gates
Belyansky, Michael P and Liu, Joyce C and Wann, Hsing Jen and Wise, Richard Stephen and Yan, Hongwen
US Patent 7,081,393
Belyansky, Michael P and Liu, Joyce C and Wann, Hsing Jen and Wise, Richard Stephen and Yan, Hongwen
US Patent 7,081,393
Etch selectivity enhancement for tunable etch resistant anti-reflective layer
Babich, Katherina E and Halle, Scott D and Horak, David V and Mahorowala, Arpan P and Natzle, Wesley C and Pfeiffer, Dirk and Yan, Hongwen
US Patent 7,077,903
Babich, Katherina E and Halle, Scott D and Horak, David V and Mahorowala, Arpan P and Natzle, Wesley C and Pfeiffer, Dirk and Yan, Hongwen
US Patent 7,077,903
2005
In-situ plasma etch for TERA hard mask materials
Wise, Richard S and Deshpande, Sadanand V and Yan, Wendy and Allen, Soctt D and Mahorowala, Arpan P
US Patent 6,903,023
Wise, Richard S and Deshpande, Sadanand V and Yan, Wendy and Allen, Soctt D and Mahorowala, Arpan P
US Patent 6,903,023
Method for reducing feature line edge roughness
Mahorowala, Arpan and Bell, Scott and Murthy, S Dakshina and Rasgon, Stacy and Yan, Hongwen and Yang, Chih-Yuh
US Patent App. 10/905,596
Mahorowala, Arpan and Bell, Scott and Murthy, S Dakshina and Rasgon, Stacy and Yan, Hongwen and Yang, Chih-Yuh
US Patent App. 10/905,596
Gate metal recess for oxidation protection and parasitic capacitance reduction
Yang, Haining and Divakaruni, Ramachandra and Gluschenkov, Oleg and Malik, Rajeev and Yan, Hongwen and Ramachandran, Ravikumar
US Patent 6,908,806
Yang, Haining and Divakaruni, Ramachandra and Gluschenkov, Oleg and Malik, Rajeev and Yan, Hongwen and Ramachandran, Ravikumar
US Patent 6,908,806
Method for reducing line edge roughness of oxide material using chemical oxide removal
Liu, Joyce C and Natzle, Wesley C and Wise, Richard S and Yan, Hongwen and Zhang, Bidan
US Patent 6,838,347
Liu, Joyce C and Natzle, Wesley C and Wise, Richard S and Yan, Hongwen and Zhang, Bidan
US Patent 6,838,347
2004
Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing
Costrini, Gregory and Hoh, Peter D and Wise, Richard S and Yan, Wendy
US Patent 6,686,296
Costrini, Gregory and Hoh, Peter D and Wise, Richard S and Yan, Wendy
US Patent 6,686,296
Oxidation sidewall image transfer patterning method
Zhang, Ying and Yan, Hongwen and Yang, Oingyun
US Patent App. 10/969,466
Zhang, Ying and Yan, Hongwen and Yang, Oingyun
US Patent App. 10/969,466
2003
Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
Tsou, Len Y and Yan, Hongwen and Yang, Qingyun and Yu, Chienfan
US Patent 6,509,219
Tsou, Len Y and Yan, Hongwen and Yang, Qingyun and Yu, Chienfan
US Patent 6,509,219
Method to controllably form notched polysilicon gate structures
Brown, Jeffrey and Wise, Richard and Yan, Hongwen and Yang, Qingyun and Yu, Chienfan
US Patent 6,541,320
Brown, Jeffrey and Wise, Richard and Yan, Hongwen and Yang, Qingyun and Yu, Chienfan
US Patent 6,541,320
2002
Magnetic mirror for preventing wafer edge damage during dry etching
Yan, Hongwen and Dobuzinsky, David and Ji, Brian and Wise, Richard
US Patent App. 10/320,842
Yan, Hongwen and Dobuzinsky, David and Ji, Brian and Wise, Richard
US Patent App. 10/320,842
Hard mask process to prevent surface roughness for selective dielectric etching
Jamison, Paul C and Wagner, Tina and Wise, Richard S and Yan, Hongwen
US Patent 6,345,399
Jamison, Paul C and Wagner, Tina and Wise, Richard S and Yan, Hongwen
US Patent 6,345,399
2001
Applying a mixture containing hexafluoroethane, a source of hydrogen selected from fluromethane, pentafluooroethane, difluoromethane, a diluent and applying high density plasma to etch antireflective coating
Armacost, Michael and Hoh, Peter and Wise, Richard S and Yan, Wendy
US Patent 6,228,279
Armacost, Michael and Hoh, Peter and Wise, Richard S and Yan, Wendy
US Patent 6,228,279
Selective dry etch of a dielectric film
Bennett, Delores A and Norum, James P and Yan, Hongwen and Yu, Chienfan
US Patent 6,294,102
Bennett, Delores A and Norum, James P and Yan, Hongwen and Yu, Chienfan
US Patent 6,294,102