Ph.D. Zuoguang (Louis) Liu  Ph.D. Zuoguang (Louis) Liu photo         

contact information

Research Staff Member
IBM Research, Albany NY USA



Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Loubet, N and Hook, T and Montanini, P and Yeung, C-W and Kanakasabapathy, S and Guillom, M and Yamashita, T and Zhang, J and Miao, X and Wang, J and others
VLSI Technology, 2017 Symposium on, pp. T230--T231

Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
Liu, Zuoguang and Gluschenkov, Oleg and Niimi, Hiroaki and Liu, Bei and Li, Juntao and Demarest, James and Mochizuki, Shogo and Adusumilli, Praneet and Raymond, Mark and Carr, Adra and others
VLSI Technology, 2017 Symposium on, pp. T212--T213

High-k metal gate fundamental learning and multi-V t options for stacked nanosheet gate-all-around transistor
Zhang, Jingyun and Ando, Takashi and Yeung, Chun Wing and Wang, Miaomiao and Kwon, Ohseong and Galatage, Rohit and Chao, Robin and Loubet, Nicolas and Moon, Bum Ki and Bao, Ruqiang and others
Electron Devices Meeting (IEDM), 2017 IEEE International, pp. 22--1

Integrated dual SPE processes with low contact resistivity for future CMOS technologies
Wu, Heng and Seo, Soon-Cheon and Niu, Chengyu and Wang, Wei and Tsutsui, Gen and Gluschenkov, Oleg and Liu, Zuoguang and Petrescu, Alexandru and Carr, Adra and Choi, Sam and others
Electron Devices Meeting (IEDM), 2017 IEEE International, pp. 22--3


A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Xie, R and Montanini, P and Akarvardar, K and Tripathi, N and Haran, B and Johnson, S and Hook, T and Hamieh, B and Corliss, D and Wang, J and others
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 2--7

Air spacer for 10nm FinFET CMOS and beyond
K Cheng, C Park, C Yeung, S Nguyen, J Zhang, X Miao, M Wang, S Mehta, J Li, C Surisetty, R Muthinti, Zuoguang Liu, H Tang, S Tsai, T Yamashita, H Bu, R Divakaruni
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 17.1. 1-17.1. 4, IEEE

Technology viable DC performance elements for Si/SiGe channel CMOS FinFET
Gen Tsutsui, Ruqiang Bao, Kwan-yong Lim, Robert R Robison, Reinaldo A Vega, Jie Yang, Zuoguang Liu, et al
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 17.4. 1-17.4. 4, IEEE

Ti and NiPt/Ti Liner Silicide Contacts for Advanced Technologie
P. Adusumilli, M. Raymond, E. Alptekin, N. Breil, F. Chafik, C. Lavoie, D. Ferrer, V. Kamineni, A. Ozcan, C. Tran, H. Utomo, H. Niimi, A. Kumar, J. Cai, V. Basker, S. Koswatta, Z. Liu, et al
2016 Symposium on VLSI Technology and Circuits (VLSI)

FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys
O Gluschenkov, Zuoguang Liu, H Niimi, S Mochizuki, J Fronheiser, X Miao, J Li, J Demarest, C Zhang, C Niu, B Liu, A Petrescu, P Adusumilli, J Yang, H Jagannathan, H Bu, T Yamashita
Electron Devices Meeting (IEDM), 2016 IEEE International, pp. 17.2. 1-17.2. 4, IEEE

Sub-10E-9 ohm-cm2 n-Type Contact Resistivity for FinFET Technology
Hiroaki Niimi, Zuoguang Liu, Oleg Gluschenkov, Shogo Mochizuki, Jody Fronheiser, Juntao Li, James Demarest, Chen Zhang, Bei Liu, Jie Yang, Mark Raymond, Bala Haran, Huiming Bu, Tenko Yamashita
IEEE Electron Device Letters 37(11), 1371-1374, IEEE, 2016


A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in FinFETs
T. Yamashita, S. Mehta, V. Basker, R. Southwick, A. Kumar, R. Kambhampati, R. Sathiyanarayanan, J. Johnson, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Zuoguang Liu, D. Lu, F. Chen, S. Khan, et. al.
2015 Symposium on VLSI Technology and Circuits (VLSI)

Separation of Interface States and Electron Trapping for Hot Carrier Degradation in Ultra-Scaled Replacement Metal Gate n-FinFETs
Miaomiao Wang, Zuoguang Liu, Tenko Yamashita, James H Stathis, Chia-yu Chen
2015 IEEE International Reliability Physics Symposium (IRPS)


Effect of hydrogen on the chemical bonding and band structure at the Al< inf> 2 O< inf> 3/In< inf> 0.53 Ga< inf> 0.47 As interface
P. Shekhter, L. Kornblum, Z. Liu, S. Cui, TP Ma, M. Eizenberg
Applied Physics Letters 99(23), 232103--232103, AIP, 2011

Effect of H on interface properties of Al< inf> 2 O< inf> 3/In< inf> 0.53 Ga< inf> 0.47 As
Z. Liu, S. Cui, P. Shekhter, X. Sun, L. Kornblum, J. Yang, M. Eizenberg, KS Chang-Liao, TP Ma
Applied Physics Letters 99(22), 222104--222104, AIP, 2011


High-Quality< formula formulatype=
S. Cui, C.Y. Peng, W. Zhang, X. Sun, J. Yang, Z. Liu, L. Kornblum, M. Eizenberg, TP Ma
Electron Device Letters, IEEE 31(12), 1443--1445, IEEE, 2010

Inelastic electron tunneling spectroscopy study of ultrathin Al 2 O 3--TiO 2 dielectric stack on Si
Z. Liu, S. Cui, L. Kornblum, M. Eizenberg, M.F. Chang, TP Ma
Applied Physics Letters 97(20), 202905--202905, AIP, 2010

Intrinsic effective mobility extraction with extremely scaled gate dielectrics
Z. Liu, D. Guo, K. Xiu, W.K. Henson, P.J. Oldiges
Applied Physics Letters 97(2), 023509--023509, AIP, 2010

A charge-trapping memory structure featuring low-voltage high-speed operation and 250° C retention
C.Y. Peng, WQ Zhang, X. Sun, ZG Liu, S. Cui, TP Ma, L. Kornblum, M. Eizenberg
Device Research Conference (DRC), 2010, pp. 261--262


Mn-doped AlN nanowires with room temperature ferromagnetic ordering
Y. Yang, Q. Zhao, XZ Zhang, ZG Liu, CX Zou, B. Shen, DP Yu
Applied Physics Letters 90(9), 092118--092118, AIP, 2007