Zehra Sura  Zehra Sura photo       

contact information

Research Scientist, Systems and Architecture for Machine Learning
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash1653

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2017

Program structure-based blocking
Bertolli, Carlo and Eichenberger, Alexandre E and O'brien, John K and Sura, Zehra N
US Patent 9,772,824
Abstract

Unaligned instruction relocation
Bertolli, Carlo and O'brien, John K and Sallenave, Olivier H and Sura, Zehra N
US Patent 9,792,098
Abstract

Schedulers with load-store queue awareness
Chen, Tong and Eichenberger, Alexandre E and Jacob, Arpith C and Sura, Zehra N
US Patent 9,563,428
Abstract

Method to efficiently implement synchronization using software managed address translation
Chen, Tong and O'brien, John Kevin and Sura, Zehra Noman
US Patent 9,658,940
Abstract


2016

Optimizing branch re-wiring in a software instruction cache
Bertolli, Carlo and O'brien, John Kevin Patrick and Eichenberger, Alexandre E and Sura, Zehra Noman
US Patent App. 14/712,253
Abstract

Accessing global data from accelerator devices
Bertolli, Carlo and O'brien, John K and Sallenave, Olivier H and Sura, Zehra N
US Patent 9,513,832
Abstract


2015

Compiler-generated memory mapping hints
O'brien, Kathryn M and O'brien, John K and Sura, Zehra N
US Patent App. 14/219,136
Abstract

Compilation and placement of instructions in a memory system
Chen, Tong and O'brien, John K and Sura, Zehra
US Patent 8,930,921
Abstract

Power-constrained compiler code generation and scheduling of work in a heterogeneous processing system
Jacobson, Hans M and Nair, Ravi and O'brien, John KP and Sura, Zehra N
US Patent 9,183,063
Abstract

Optimized division of work among processors in a heterogeneous processing system
Chen, Tong and O'brien, John KP and Sura, Zehra N
US Patent 8,997,071
Abstract


2014

Data placement for execution of an executable
Chen, Tong and O'brien, John K and Sura, Zehra
US Patent 8,914,778
Abstract


2013

Target memory hierarchy specification in a multi-core computer processing system
Chen, Tong and Gao, Yaoqing and O'brien, Kevin K and Sura, Zehra N and Zhang, Lixin
US Patent 8,495,307
Abstract

Data transfer optimized software cache for regular memory references
Ayguade, Eduard and Chen, Tong and Eichenberger, Alexandre E and Tallada, Marc Gonzalez and Martorell, Xavier and O'brien, John K and O'brien, Kathryn M and Sura, Zehra N and Zhang, Tao and others
US Patent 8,527,974
Abstract

Optimized code generation targeting a high locality software cache
Chen, Tong and Eichenberger, Alexandre E and Tallada, Marc Gonzalez and O'brien, John K and O'brien, Kathryn M and Sura, Zehra N and Zhang, Tao
US Patent 8,561,044
Abstract


2012

Compiler implemented software cache in which non-aliased explicitly fetched data are excluded
Chen, Tong and O'brien, John Kevin Patrick and O'brien, Kathryn and So, Byoungro and Sura, Zehra N and Zhang, Tao
US Patent 8,214,816
Abstract

Prefetching irregular data references for software controlled caches
Chen, Tong and Tallada, Marc Gonzalez and Sura, Zehra N and Zhang, Tao
US Patent 8,239,841
Abstract

Dynamically controlling a prefetching range of a software controlled cache
Chen, Tong and Tallada, Marc Gonzalez and Sura, Zehra N and Zhang, Tao
US Patent 8,146,064
Abstract


2011

Managing speculative assist threads
Archambault, Roch G and Chen, Tong and Gao, Yaoqing and Mohammed, Khaled A and O'brien, John K and Pekhimenko, Gennady and Silvera, Raul E and Sura, Zehra N
US Patent App. 12/905,202
Abstract

Reducing cache pollution of a software controlled cache
Chen, Tong and Tallada, Marc Gonzalez and Sura, Zehra N and Zhang, Tao
US Patent 8,055,849
Abstract


2010


Method and apparatus for application-specific dynamic cache placement
Kailas, Krishnan Kunjunny and Ravindran, Rajiv Alazhath and Sura, Zehra
US Patent 7,836,256
Abstract

Compiler implemented software cache method in which non-aliased explicitly fetched data are excluded
Chen, Tong and O'brien, John Kevin Patrick and O'brien, Kathryn and So, Byoungro and Sura, Zehra N and Zhang, Tao
US Patent 7,784,037
Abstract



2009

Method and apparatus for dynamic priority-based cache replacement
Kailas, Krishnan Kunjunny and Ravindran, Rajiv Alazhath and Sura, Zehra
US Patent 7,502,890
Abstract


2008

Compiler assisted re-configurable software implemented cache
Chen, Tong and O'brien, John Kevin Patrick and O'brien, Kathryn M and So, Byoungro and Sura, Zehra N and Zhang, Tao
US Patent App. 11/427,790
Abstract