Kubilay Atasu 
contact information
Research Staff MemberZurich Research Laboratory, Zurich, Switzerland +41
447248752
447248752 links
Professional Associations
Professional Associations: ACM | IEEE, Senior Membermore information
More information: Google Scholar Profile2018
Tera-Scale Coordinate Descent on GPUs
T. Parnell, C. Duenner, K. Atasu, M. Sifalakis, H. Pozidis
Future Generation Computer Systems, 2018
T. Parnell, C. Duenner, K. Atasu, M. Sifalakis, H. Pozidis
Future Generation Computer Systems, 2018
Faster Text Similarity Using a Linear-Complexity Relaxed Word Mover's Distance
Atasu, Kubilay and Vasileiadis, Vasileios and Vlachos, Michail
ERCIM NEWS (112), 38--39, 2018
Atasu, Kubilay and Vasileiadis, Vasileios and Vlachos, Michail
ERCIM NEWS (112), 38--39, 2018
Addressing Interpretability and Cold-Start in Matrix Factorization for Recommender Systems
Vlachos, Michail and Duenner, Celestine and Heckel, Reinhard and Vassiliadis, Vassilios G and Parnell, Thomas and Atasu, Kubilay
IEEE Transactions on Knowledge and Data Engineering, IEEE, 2018
Vlachos, Michail and Duenner, Celestine and Heckel, Reinhard and Vassiliadis, Vassilios G and Parnell, Thomas and Atasu, Kubilay
IEEE Transactions on Knowledge and Data Engineering, IEEE, 2018
GPU-Accelerated Semantic Similarity Search at Scale
K. Atasu et al.
GPU Technology Conference, 2018
slides
K. Atasu et al.
GPU Technology Conference, 2018
slides
2017
Understanding and optimizing the performance of distributed machine learning applications on apache spark
C. Duenner, T. Parnell, K. Atasu, M. Sifalakis, H. Pozidis
Big Data (Big Data), 2017 IEEE International Conference on, pp. 331--338
C. Duenner, T. Parnell, K. Atasu, M. Sifalakis, H. Pozidis
Big Data (Big Data), 2017 IEEE International Conference on, pp. 331--338
High-Performance Recommender System Training Using Co-Clustering on CPU/GPU Clusters
K. Atasu, T. Parnell, C. Duenner, M. Vlachos, H. Pozidis
The 46th International Conference on Parallel Processing (ICPP), 2017
K. Atasu, T. Parnell, C. Duenner, M. Vlachos, H. Pozidis
The 46th International Conference on Parallel Processing (ICPP), 2017
Linear-Complexity Relaxed Word Mover's Distance with GPU Acceleration
K. Atasu et al.
IEEE International Conference on Big Data , 2017
K. Atasu et al.
IEEE International Conference on Big Data , 2017
Large-Scale Stochastic Learning using GPUs
T. Parnell, C. Duenner, K. Atasu, M. Sifalakis, H. Pozidis
The 6th International Workshop on Parallel and Distributed Computing for Large Scale Machine Learning and Big Data Analytics (ParLearning 2017)
T. Parnell, C. Duenner, K. Atasu, M. Sifalakis, H. Pozidis
The 6th International Workshop on Parallel and Distributed Computing for Large Scale Machine Learning and Big Data Analytics (ParLearning 2017)
Foreword to the Special Section on Reconfigurable Computing
Derrien, Steven and Atasu, Kubilay and Cardoso, Jo{\~a}o MP and Becker, Juergen
Journal of Signal Processing Systems, 1--3, Springer, 2017
Abstract
Derrien, Steven and Atasu, Kubilay and Cardoso, Jo{\~a}o MP and Becker, Juergen
Journal of Signal Processing Systems, 1--3, Springer, 2017
Abstract
A hardware compilation framework for text analytics queries
Polig, Raphael and Atasu, Kubilay and Giefers, Heiner and Hagleitner, Christoph and Chiticariu, Laura and Reiss, Frederick and Zhu, Huaiyu and Hofstee, Peter
Journal of Parallel and Distributed Computing, Elsevier, 2017
Polig, Raphael and Atasu, Kubilay and Giefers, Heiner and Hagleitner, Christoph and Chiticariu, Laura and Reiss, Frederick and Zhu, Huaiyu and Hofstee, Peter
Journal of Parallel and Distributed Computing, Elsevier, 2017
2016
Annotation-based finite-state transducers on reconfigurable devices
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama
Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, pp. 1--9
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama
Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, pp. 1--9
High-Performance Distributed Machine Learning using Apache SPARK
Duenner, Celestine and Parnell, Thomas and Atasu, Kubilay and Sifalakis, Manolis and Pozidis, Haralampos
arXiv preprint arXiv:1612.01437, 2016
Duenner, Celestine and Parnell, Thomas and Atasu, Kubilay and Sifalakis, Manolis and Pozidis, Haralampos
arXiv preprint arXiv:1612.01437, 2016
2015
The Golden Age of FPGAs
Kubilay Atasu
The International Conference on Field-programmable Logic and Applications (FPL) , 2015
Kubilay Atasu
The International Conference on Field-programmable Logic and Applications (FPL) , 2015
Leftmost Longest Regular Expression Matching in Reconfigurable Logic
Kubilay Atasu.
The 2015 International Conference on Field-Programmable Technology (FPT '15), pp. 17-23, IEEE
slides
Kubilay Atasu.
The 2015 International Conference on Field-Programmable Technology (FPT '15), pp. 17-23, IEEE
slides
Feature-rich regular expression matching accelerator for text analytics
Atasu, Kubilay
Journal of Signal Processing Systems, 1--17, Springer, 2015
Atasu, Kubilay
Journal of Signal Processing Systems, 1--17, Springer, 2015
Accelerating Text Analytics Queries on Reconfigurable Platforms
Atasu, Kubilay and Polig, Raphael and Hagleitner, Christoph and Hofstee, H Peter and Chiticariu, Laura and Reiss, Frederick and Zhu, Huaiyu and Berrospi, Cesar
Workshop. CARL, 2015
slides
Atasu, Kubilay and Polig, Raphael and Hagleitner, Christoph and Hofstee, H Peter and Chiticariu, Laura and Reiss, Frederick and Zhu, Huaiyu and Berrospi, Cesar
Workshop. CARL, 2015
slides
2014
Guest Editorial: Application Specific Processors and Architectures
Smith, Melissa C and Atasu, Kubilay
Journal of Signal Processing Systems 77(1-2), 1--3, Springer, 2014
Abstract
Smith, Melissa C and Atasu, Kubilay
Journal of Signal Processing Systems 77(1-2), 1--3, Springer, 2014
Abstract
Hardware-accelerated text analytics
R. Polig, K. Atasu, C. Hagleitner, L. Chiticariu, H. Zhu, F. Reiss, H. P. Hofstee
Hot Chips: A Symposium on High Performance Chips, 2014
R. Polig, K. Atasu, C. Hagleitner, L. Chiticariu, H. Zhu, F. Reiss, H. P. Hofstee
Hot Chips: A Symposium on High Performance Chips, 2014
Compiling text analytics queries to FPGAs
Polig, Raphael and Atasu, Kubilay and Giefers, Heiner and Chiticariu, Laura
2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp. 1--6
Polig, Raphael and Atasu, Kubilay and Giefers, Heiner and Chiticariu, Laura
2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp. 1--6
Giving text analytics a boost
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H Peter Hofstee, Frederick R Reiss, Huaiyu Zhu, Eva Sitaridi
IEEE Micro 34(4), 6--14, IEEE, 2014
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H Peter Hofstee, Frederick R Reiss, Huaiyu Zhu, Eva Sitaridi
IEEE Micro 34(4), 6--14, IEEE, 2014
Resource-efficient regular expression matching architecture for text analytics
Kubilay Atasu
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, pp. 1--8
slides
Kubilay Atasu
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, pp. 1--8
slides
2013
Hardware-accelerated regular expression matching for high-throughput text analytics
Atasu, Kubilay and Polig, Raphael and Hagleitner, Christoph and Reiss, Frederick R
2013 23rd International Conference on Field programmable Logic and Applications, pp. 1--7
slides
Atasu, Kubilay and Polig, Raphael and Hagleitner, Christoph and Reiss, Frederick R
2013 23rd International Conference on Field programmable Logic and Applications, pp. 1--7
slides
Exploring the design space of programmable regular expression matching accelerators
Atasu, Kubilay and Polig, Raphael and Rohrer, Jonathan and Hagleitner, Christoph
Journal of Systems Architecture 59(10), 1184--1196, Elsevier, 2013
Atasu, Kubilay and Polig, Raphael and Rohrer, Jonathan and Hagleitner, Christoph
Journal of Systems Architecture 59(10), 1184--1196, Elsevier, 2013
Hardware-accelerated regular expression matching with overlap handling on IBM PowerEN processor
Atasu, Kubilay and Doerfler, Florian and van Lunteren, Jan and Hagleitner, Christoph
Parallel & Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pp. 1254--1265
slides
Atasu, Kubilay and Doerfler, Florian and van Lunteren, Jan and Hagleitner, Christoph
Parallel & Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pp. 1254--1265
slides
Token-based dictionary pattern matching for text analytics
Polig, Raphael and Atasu, Kubilay and Hagleitner, Christoph
2013 23rd International Conference on Field programmable Logic and Applications, pp. 1--6
Polig, Raphael and Atasu, Kubilay and Hagleitner, Christoph
2013 23rd International Conference on Field programmable Logic and Applications, pp. 1--6
2012
Designing a programmable wire-speed regular-expression matching accelerator
Van Lunteren, Jan and Hagleitner, Christoph and Heil, Timothy and Biran, Giora and Shvadron, Uzi and Atasu, Kubilay
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 461--472
Van Lunteren, Jan and Hagleitner, Christoph and Heil, Timothy and Biran, Giora and Shvadron, Uzi and Atasu, Kubilay
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 461--472
Proving correctness of regular expression accelerators
M. Purandare, K. Atasu, C. Hagleitner
Design Automation Conference, pp. 350-355, 2012
M. Purandare, K. Atasu, C. Hagleitner
Design Automation Conference, pp. 350-355, 2012
FISH: Fast instruction synthesis for custom processors
Atasu, Kubilay and Luk, Wayne and Mencer, Oskar and Ozturan, Can and Dundar, G{
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20(1), 52--65, IEEE, 2012
Atasu, Kubilay and Luk, Wayne and Mencer, Oskar and Ozturan, Can and Dundar, G{
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20(1), 52--65, IEEE, 2012
Complexity of computing convex subgraphs in custom instruction synthesis
Reddington, Joseph and Atasu, Kubilay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20(12), 2337--2341, IEEE, 2012
author copy
Reddington, Joseph and Atasu, Kubilay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20(12), 2337--2341, IEEE, 2012
author copy
2009
Memory-efficient distribution of regular expressions for fast deep packet inspection
Rohrer, Jonathan and Atasu, Kubilay and van Lunteren, Jan and Hagleitner, Christoph
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pp. 147--154, 2009
Rohrer, Jonathan and Atasu, Kubilay and van Lunteren, Jan and Hagleitner, Christoph
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pp. 147--154, 2009
Regular expression acceleration at multiple tens of Gb/s
Van Lunteren, Jan and Rohrer, Jon and Atasu, Kubilay and Hagleitner, Christoph
1st Workshop on Accelerators for High-performance Architectures in conjunction with ICS, 2009
Van Lunteren, Jan and Rohrer, Jon and Atasu, Kubilay and Hagleitner, Christoph
1st Workshop on Accelerators for High-performance Architectures in conjunction with ICS, 2009
2008
Optimal implementation of combinational logic on look-up tables
Atasu, Kubilay and Todman, Tim and Mencer, Oskar and Luk, Wayne
Research in Microelectronics and Electronics, 2008. PRIME 2008. Ph. D., pp. 153--156
Abstract
Atasu, Kubilay and Todman, Tim and Mencer, Oskar and Luk, Wayne
Research in Microelectronics and Electronics, 2008. PRIME 2008. Ph. D., pp. 153--156
Abstract
Fast custom instruction identification by convex subgraph enumeration
Atasu, Kubilay and Mencer, Oskar and Luk, Wayne and Ozturan, Can and Dundar, Gunhan
2008 International Conference on Application-Specific Systems, Architectures and Processors, pp. 1--6
Abstract
Atasu, Kubilay and Mencer, Oskar and Luk, Wayne and Ozturan, Can and Dundar, Gunhan
2008 International Conference on Application-Specific Systems, Architectures and Processors, pp. 1--6
Abstract
CHIPS: Custom hardware instruction processor synthesis
Atasu, Kubilay and Ozturan, Can and Dundar, G{"U}nhan and Mencer, Oskar and Luk, Wayne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(3), 528--541, IEEE, 2008
Abstract
Atasu, Kubilay and Ozturan, Can and Dundar, G{"U}nhan and Mencer, Oskar and Luk, Wayne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(3), 528--541, IEEE, 2008
Abstract
2007
Hardware/software partitioning for custom instruction processors
Atasu, Kubilay
Ph.D. Thesis, 2007
Abstract
Atasu, Kubilay
Ph.D. Thesis, 2007
Abstract
Optimizing instruction-set extensible processors under data bandwidth constraints
Atasu, Kubilay and Dimond, Robert G and Mencer, Oskar and Luk, Wayne and Ozturan, Can and Dundar, Gunhan
2007 Design, Automation & Test in Europe Conference & Exhibition, pp. 1--6
Abstract
Atasu, Kubilay and Dimond, Robert G and Mencer, Oskar and Luk, Wayne and Ozturan, Can and Dundar, Gunhan
2007 Design, Automation & Test in Europe Conference & Exhibition, pp. 1--6
Abstract
2006
Accelerating scientific computations using fpgas
Pell, Oliver and Howes, Lee W and Atasu, Kubilay and Beckmann, Olav and Mencer, Oskar
The Advanced Maui Optical and Space Surveillance Technologies Conference, pp. 97, 2006
Abstract
Pell, Oliver and Howes, Lee W and Atasu, Kubilay and Beckmann, Olav and Mencer, Oskar
The Advanced Maui Optical and Space Surveillance Technologies Conference, pp. 97, 2006
Abstract
Towards Optimal Custom Instruction Processors
W. Luk, K. Atasu, R. Dimond and O. Mencer
IEEE HOT Chips Conference, 2006
W. Luk, K. Atasu, R. Dimond and O. Mencer
IEEE HOT Chips Conference, 2006
Exact and approximate algorithms for the extension of embedded processor instruction sets
Pozzi, Laura and Atasu, Kubilay and Ienne, Paolo
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(7), 1209--1229, IEEE, 2006
Abstract
Pozzi, Laura and Atasu, Kubilay and Ienne, Paolo
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(7), 1209--1229, IEEE, 2006
Abstract
2005
An integer linear programming approach for identifying instruction-set extensions
Atasu, Kubilay and D{"u}ndar, G{"u}nhan and {"O}zturan, Can
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 172--177, 2005
Abstract
Atasu, Kubilay and D{"u}ndar, G{"u}nhan and {"O}zturan, Can
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 172--177, 2005
Abstract
2004
Efficient AES implementations for ARM based platforms
Atasu, Kubilay and Breveglieri, Luca and Macchetti, Marco
Proceedings of the 2004 ACM symposium on Applied computing, pp. 841--845
Abstract
Atasu, Kubilay and Breveglieri, Luca and Macchetti, Marco
Proceedings of the 2004 ACM symposium on Applied computing, pp. 841--845
Abstract
Introduction of local memory elements in instruction set extensions
Biswas, Partha and Choudhary, Vinay and Atasu, Kubilay and Pozzi, Laura and Ienne, Paolo and Dutt, Nikil
Proceedings of the 41st annual Design Automation Conference, pp. 729--734, 2004
Abstract
Biswas, Partha and Choudhary, Vinay and Atasu, Kubilay and Pozzi, Laura and Ienne, Paolo and Dutt, Nikil
Proceedings of the 41st annual Design Automation Conference, pp. 729--734, 2004
Abstract
2003
Automatic application-specific instruction-set extensions under microarchitectural
constraints
Kubilay Atasu, Laura Pozzi, Paolo Ienne
Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 256--261
Kubilay Atasu, Laura Pozzi, Paolo Ienne
Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 256--261
Automatic application-specific instruction-set extensions under microarchitectural constraints
Atasu, Kubilay and Pozzi, Laura and Ienne, Paolo
International Journal of Parallel Programming 31(6), 411--428, Springer, 2003
Abstract
Atasu, Kubilay and Pozzi, Laura and Ienne, Paolo
International Journal of Parallel Programming 31(6), 411--428, Springer, 2003
Abstract