Martin Schmatz
contact information
KeyProtect Technologies & IoT Edge Computing, Member IBM AoTZurich Research Laboratory, Zurich, Switzerland +41
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Professional Associations
Professional Associations: IEEE, Senior Membermore information
More information: Systems department2015
Persistent caching for operating a persistent caching system
Bernard Metzler, Martin L. Schmatz, Patrick Stuedi, Animesh K. Trivedi
Patent US 20,150,113,088 A1
Bernard Metzler, Martin L. Schmatz, Patrick Stuedi, Animesh K. Trivedi
Patent US 20,150,113,088 A1
2014
Apparatus and method for accessing a memory device
Peter Buchmann, Martin Leo Schmatz, Jan van Lunteren
Patent US 8,645,620 B2
Peter Buchmann, Martin Leo Schmatz, Jan van Lunteren
Patent US 8,645,620 B2
Inductor combining primary and secondary coils with phase shifting
Marcel A. Kossel, Thomas E. Morf, Martin Leo Schmatz, Jonas R. Weiss
Patent US 8,717,138 B2
Marcel A. Kossel, Thomas E. Morf, Martin Leo Schmatz, Jonas R. Weiss
Patent US 8,717,138 B2
Optimization of virtual machine sizing and consolidation
Robert Birke, Yiyu L. Chen, Martin L. Schmatz
Patent US 20,140,215,464 A1
Robert Birke, Yiyu L. Chen, Martin L. Schmatz
Patent US 20,140,215,464 A1
2013
Memory module and memory controller for controlling a memory module
Andreas C. Doering, Patricia M. Sagmeister, Martin L. Schmatz
Patent US 20,130,124,786 A1
Andreas C. Doering, Patricia M. Sagmeister, Martin L. Schmatz
Patent US 20,130,124,786 A1
Distributed memory access in a network
Patrick Droz, Antonius P. Engbersen, Christoph Hagleitner, Ronald P. Luijten, Bernard Metzler, Martin L. Schmatz, Patrick Stuedi, Animesh Kumar Trivedi
Patent US 20,130,326,122 A1
Patrick Droz, Antonius P. Engbersen, Christoph Hagleitner, Ronald P. Luijten, Bernard Metzler, Martin L. Schmatz, Patrick Stuedi, Animesh Kumar Trivedi
Patent US 20,130,326,122 A1
Memory sharing by processors
Victoria Caparros Cabezas, Rik Jongerius, Martin L. Schmatz, Phillip Stanley-Marbell
Patent US 20,130,159,632 A1
Victoria Caparros Cabezas, Rik Jongerius, Martin L. Schmatz, Phillip Stanley-Marbell
Patent US 20,130,159,632 A1
Inductor combining primary and secondary coils with phase shifting
Marcel A. Kossel, Thomas E. Morf, Martin Leo Schmatz, Jonas R. Weiss
Patent US 8,421,573 B2
Marcel A. Kossel, Thomas E. Morf, Martin Leo Schmatz, Jonas R. Weiss
Patent US 8,421,573 B2
Structure for a reference voltage generator for analog to digital converters
Lukas Kull, Martin L. Schmatz
Patent US 8,436,677 B2
Lukas Kull, Martin L. Schmatz
Patent US 8,436,677 B2
Error correcting code protected quasi-static bit communication on a high-speed bus
Peter Buchmann, Kevin C. Gower, Robert J. Reese, Martin L. Schmatz, Michael R. Trombley
Patent US 8,516,338 B2
Peter Buchmann, Kevin C. Gower, Robert J. Reese, Martin L. Schmatz, Michael R. Trombley
Patent US 8,516,338 B2
Off-line gain calibration in a time-interleaved analog-to-digital converter
Anthony R. Bonaccio, Frank R. Keyser, III, Martin L. Schmatz, Benjamin T. Voegli
Patent US 8,587,464 B2
Anthony R. Bonaccio, Frank R. Keyser, III, Martin L. Schmatz, Benjamin T. Voegli
Patent US 8,587,464 B2
2012
Method and apparatus for handling of clock information in serial link ports
Peter Buchmann, Martin Leo Schmatz
Patent US 8,149,979 B2
Peter Buchmann, Martin Leo Schmatz
Patent US 8,149,979 B2
Method and arrangements for link power reduction
Hayden Clavie Cranford, Jr., Gareth John Nicholls, Vernon Roberts Norman, Martin Leo Schmatz, Karl David Selander, Michael Anthony Sorna
Patent US 8,130,887 B2
Hayden Clavie Cranford, Jr., Gareth John Nicholls, Vernon Roberts Norman, Martin Leo Schmatz, Karl David Selander, Michael Anthony Sorna
Patent US 8,130,887 B2
Power-on initialization and test for a cascade interconnect memory system
Peter L. Buchmann, Frank D. Ferraiolo, Kevin C. Gower, Robert J. Reese, Eric E. Retter, Martin L. Schmatz, Michael B. Spear, Peter M. Thomsen, Michael R. Trombley
Patent US 8,139,430 B2
Peter L. Buchmann, Frank D. Ferraiolo, Kevin C. Gower, Robert J. Reese, Eric E. Retter, Martin L. Schmatz, Michael B. Spear, Peter M. Thomsen, Michael R. Trombley
Patent US 8,139,430 B2
2011
Continuously tunable inductor and method to continuously tune an inductor
M A Kossel, T E Morf, M L Schmatz, J R Weiss
US Patent 8,044,732
M A Kossel, T E Morf, M L Schmatz, J R Weiss
US Patent 8,044,732
Apparatus for transmitting data and additional information simultaneously within a wire-based communication system
H C Cranford Jr, M Schmatz
US Patent 8,054,867
H C Cranford Jr, M Schmatz
US Patent 8,054,867
Low-power, low-area high-speed receiver architecture
Christoph Hagleitner, Christian I Menolfi, Martin L Schmatz, Thomas H Toifl
US Patent 7,885,365
Christoph Hagleitner, Christian I Menolfi, Martin L Schmatz, Thomas H Toifl
US Patent 7,885,365
Inductor and method of operating an inductor by combining primary and secondary coils with coupling structures
M A Kossel, T E Morf, M L Schmatz, J R Weiss
US Patent 8,018,312
M A Kossel, T E Morf, M L Schmatz, J R Weiss
US Patent 8,018,312
Clock and data recovery system and method for clock and data recovery based on a forward error correction
H.C. Cranford Jr, M.L. Schmatz, T.H. Toifl, others
US Patent 8,054,926
H.C. Cranford Jr, M.L. Schmatz, T.H. Toifl, others
US Patent 8,054,926
2010
Using statistical signatures for testing high-speed circuits
H C Cranford Jr, V R Norman, M L Schmatz, others
US Patent 7,661,052
H C Cranford Jr, V R Norman, M L Schmatz, others
US Patent 7,661,052
One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery
J A Carballo, H C Cranford Jr, G J Nicholls, V R Norman, M L Schmatz
US Patent 7,809,054
J A Carballo, H C Cranford Jr, G J Nicholls, V R Norman, M L Schmatz
US Patent 7,809,054
Method and apparatus for handling of clock information in serial link ports
P Buchmann, M L Schmatz
US Patent 7,684,534
P Buchmann, M L Schmatz
US Patent 7,684,534
Phase locked loop and method for adjusting the frequency and phase in the phase locked loop
M A Kossel, T E Morf, M L Schmatz, S Wehrli
US Patent 7,839,221
M A Kossel, T E Morf, M L Schmatz, S Wehrli
US Patent 7,839,221
2009
COMMUNICATION SYSTEM WITH DATA SCRAMBLING RATE CONTROL
F FERRAIOLO, D DREPS, R REESE, M SCHMATZ
WO Patent WO/2009/100,976
F FERRAIOLO, D DREPS, R REESE, M SCHMATZ
WO Patent WO/2009/100,976
INDUCTOR COMBINING PRIMARY AND SECONDARY COILS WITH PHASE SHIFTING
M A Kossel, T E Morf, M L Schmatz, J R Weiss
US Patent App. 12/367,008
M A Kossel, T E Morf, M L Schmatz, J R Weiss
US Patent App. 12/367,008
CIRCUIT FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN HIGH SPEED SERIAL LINKS
H C Cranford Jr, G J Nicholls, B Modaress-razavi, V R Norman, M L Schmatz
US Patent App. 12/349,385
H C Cranford Jr, G J Nicholls, B Modaress-razavi, V R Norman, M L Schmatz
US Patent App. 12/349,385
Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods
P Buchmann, M L Schmatz
US Patent 7,492,807
P Buchmann, M L Schmatz
US Patent 7,492,807
method for providing automatic adaptation to frequency offsets in high speed serial links
H C Cranford Jr, G J Nicholls, B Modaress-Razavi, V R Norman, M L Schmatz, others
US Patent 7,477,713
H C Cranford Jr, G J Nicholls, B Modaress-Razavi, V R Norman, M L Schmatz, others
US Patent 7,477,713
Method and system for low-power integrating decision feedback equalizer with fast switched-capacitor feed forward path
T.H. Toifl, M.L. Schmatz, C.I. Menolfi, others
US Patent 7,539,243
T.H. Toifl, M.L. Schmatz, C.I. Menolfi, others
US Patent 7,539,243
System, method and storage medium for deriving clocks in a memory system
F D Ferraiolo, K C Gower, M L Schmatz
US Patent 7,478,259
F D Ferraiolo, K C Gower, M L Schmatz
US Patent 7,478,259
2008
ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS
P Buchmann, K C Gower, R J Reese, M L Schmatz, M R Trombley
US Patent App. 12/165,788
P Buchmann, K C Gower, R J Reese, M L Schmatz, M R Trombley
US Patent App. 12/165,788
Communications System via Data Scrambling and Associated Methods
D M Dreps, F D Ferralolo, R J Reese, M L Schmatz
US Patent App. 12/028,953
D M Dreps, F D Ferralolo, R J Reese, M L Schmatz
US Patent App. 12/028,953
POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY SYSTEM
P L Buchmann, F D Ferraiolo, K C Gower, R J Reese, E E Retter, M L Schmatz, M B Spear, P M Thomsen, M R Trombley
US Patent App. 12/166,139
P L Buchmann, F D Ferraiolo, K C Gower, R J Reese, E E Retter, M L Schmatz, M B Spear, P M Thomsen, M R Trombley
US Patent App. 12/166,139
STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY
J A Carballo, H C Cranford, G J Nicholls, V R Norman, M L Schmatz
US Patent App. 12/138,214
J A Carballo, H C Cranford, G J Nicholls, V R Norman, M L Schmatz
US Patent App. 12/138,214
Methods and arrangements for link power reduction
H C Cranford Jr, G J Nicholls, V R Norman, M L Schmatz, K D Selander, M A Sorna, others
US Patent 7,397,876
H C Cranford Jr, G J Nicholls, V R Norman, M L Schmatz, K D Selander, M A Sorna, others
US Patent 7,397,876
ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY
H C Cranford, R Kelkar, A R Malladi, M L Schmatz, N A Shah
US Patent App. 12/100,485
H C Cranford, R Kelkar, A R Malladi, M L Schmatz, N A Shah
US Patent App. 12/100,485
Method and Arrangements for Link Power Reduction
H C Cranford, G J Nicholls, V R Norman, M L Schmatz, K D Selander, M A Sorna, others
US Patent App. 12/124,106
H C Cranford, G J Nicholls, V R Norman, M L Schmatz, K D Selander, M A Sorna, others
US Patent App. 12/124,106
Digital adaptive control loop for data deserialization
H C Cranford Jr, V R Norman, M L Schmatz, others
US Patent 7,317,777
H C Cranford Jr, V R Norman, M L Schmatz, others
US Patent 7,317,777
System and method for transmitting data and additional information simultaneously within a wire based communication system
H C Cranford Jr, M Schmatz
US Patent 7,346,094
H C Cranford Jr, M Schmatz
US Patent 7,346,094
2007
Transmitter-receiver crossbar for a packet switch
W E Denzel, R P Luijten, T E Morf, M L Schmatz
US Patent App. 11/803,803
W E Denzel, R P Luijten, T E Morf, M L Schmatz
US Patent App. 11/803,803
Systems and Apparatus for Providing a Multi-Mode Memory Interface
P. Buchmann, C.I. Menolfi, M.L. Schmatz, T.H. Toifl, J.R. Weiss
US Patent App. 11/834,926
P. Buchmann, C.I. Menolfi, M.L. Schmatz, T.H. Toifl, J.R. Weiss
US Patent App. 11/834,926
Method for determining jitter of a signal in a serial link and high speed serial link
H C Cranford Jr, M A Kossel, V R Norman, M L Schmatz, others
US Patent 7,295,604
H C Cranford Jr, M A Kossel, V R Norman, M L Schmatz, others
US Patent 7,295,604
2006
PLL WITH PHASE ROTATOR
H C Cranford, S J Garvin, V R Norman, P A Owczarski, M L Schmatz, J M Stevens
EP Patent 1,352,475
H C Cranford, S J Garvin, V R Norman, P A Owczarski, M L Schmatz, J M Stevens
EP Patent 1,352,475
Dynamic measurement of communication channel characteristics using direct sequence spread spectrum (DSSS) systems, methods and program products
C E Aust, H C Cranford Jr, M L Schmatz, others
US Patent 7,088,766
C E Aust, H C Cranford Jr, M L Schmatz, others
US Patent 7,088,766
Phase rotator and data recovery receiver incorporating said phase rotator
M Schmatz, others
US Patent 7,050,522
M Schmatz, others
US Patent 7,050,522
Systems and Arrangements for Controlling an Impedance on a Transmission Path
H.C. Cranford, D.J. Friedman, J.S. Mason, M.L. Schmatz, M.A. Sorna, T.H. Toifl
US Patent App. 11/557,676
H.C. Cranford, D.J. Friedman, J.S. Mason, M.L. Schmatz, M.A. Sorna, T.H. Toifl
US Patent App. 11/557,676
Architecture for advanced serial link between two cards
H C Cranford Jr, V R Norman, M L Schmatz
US Patent 7,082,484
H C Cranford Jr, V R Norman, M L Schmatz
US Patent 7,082,484
Apparatus and method for oversampling with evenly spaced samples
H C Cranford Jr, V R Norman, M L Schmatz, others
US Patent 6,999,544
H C Cranford Jr, V R Norman, M L Schmatz, others
US Patent 6,999,544
Analog unidirectional serial link architecture
H C Cranford Jr, S J Garvin, V R Norman, P A Owczarski, M L Schmatz, J M Stevens, others
US Patent 7,142,624
H C Cranford Jr, S J Garvin, V R Norman, P A Owczarski, M L Schmatz, J M Stevens, others
US Patent 7,142,624
Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery
H C Cranford Jr, V R Norman, M Schmatz
US Patent 7,149,269
H C Cranford Jr, V R Norman, M Schmatz
US Patent 7,149,269
2005
2004
Optical land grid array interposer
S R Howland, J U Knickerbocker, S P Ostrander, M L Schmatz
US Patent 6,819,813
S R Howland, J U Knickerbocker, S P Ostrander, M L Schmatz
US Patent 6,819,813
Phase rotator, phase rotation method and clock and data recovery receiver incorporating said phase rotator
H C Cranford, M R Cordrey-Gal, J S Mason, P J Murfet, G J Nicholls, T M Rasmus, M L Schmatz, P R Seidel
US Patent App. 10/769,437
H C Cranford, M R Cordrey-Gal, J S Mason, P J Murfet, G J Nicholls, T M Rasmus, M L Schmatz, P R Seidel
US Patent App. 10/769,437