Nikolaos Papandreou  Nikolaos Papandreou photo         

contact information

Research Staff Member
IBM Research - Zurich, Switzerland
  +41dash44dash724dash87dash38

links

Professional Associations

Professional Associations:  IEEE, Senior Member

more information

More information:   Google Scholar Citations


2021

Migrating data between block pools in a storage system
S. Tomic, R. Stoica, N. Papandreou, N. Ioannou, R. Pletka, A. Fry, T. Fisher
US Patent 11,138,124

Dynamically adjusting block mode pool sizes
R. Stoica, R. Pletka, N. Ioannou, N. Papandreou, S. Tomic
US Patent 11,126,360

Error recovery of data in non-volatile memory during read
N. Ioannou, H. Pozidis, S. Tomic, N. Papandreou, R. Pletka, A. Fry, T. Fisher
US Patent 11,120,882

Selectively storing parity data in different types of memory
N. Ioannou, T. Fisher, R. Pletka, N. Papandreou, R. Stoica, S. Tomic, A. Fry
US Patent 11,119,855

Selective page calibration based on hierarchical page mapping
N. Papandreou, S. Tomic, R. Pletka, N. Ioannou, H. Pozidis, A. Fry, T. Fisher
US Patent 11,094,383

Managing the reliability of pages in non-volatile random access memory
N. Papandreou, R. Pletka, S. Tomic, N. Ioannou, H. Pozidis, T. Fisher, A. Fry
US Patent 11,086,705

Reducing effects of read array operations of read apparent voltage
K. Sallese, T. Fisher, A. Yanes, J. Ma, C. Keller, A. Fry, V. Huynh, N. Papandreou
US Patent 11,086,565

Updating corrective read voltage offsets in non-volatile random access memory
N. Papandreou, H. Pozidis, N. Ioannou, R. Pletka, R. Stoica, S. Tomic, A. Fry, T. Fisher
US Patent 11,056,199

Selectively performing multi-plane read operations in non-volatile memory
N. Ioannou, N. Papandreou, R. Pletka, S. Tomic, H. Pozidis, A. Fry, T. Fisher, K. Sallese
US Patent 11,048,571

Managing memory block calibration based on priority levels
N. Papandreou, R. Pletka, A. Fry, T. Fisher, N. Ioannou, H. Pozidis, R. Stoica, S. Tomic
US Patent 11,036,415

Block mode toggling using hybrid controllers
R. Pletka, A. Fry, T. Fisher, S. Tomic, N. Papandreou, N. Ioannou, H. Pozidis, A. Walls
US Patent 11,023,150

Block health estimation for wear leveling in non-volatile memories
R. Pletka, S.Tomic, N. Papandreou, N. Ioannou, A. Fry, T. Fisher
US Patent 11,016,693

Virtual to physical translation and media repair in storage class memory
R. Galbraith, D. Jamsek, A. Martin, D. Moertl, M. Negussie, T. Mittelholzer, N. Papandreou, H. Pozidis, M. Stanisavljevic
US Patent 10,997,084

Data placement in write cache architecture supporting read heat data separation
R. Pletka, T. Fisher, A. Fry, N. Papandreou, N. Ioannou, S. Tomic, R. Stoica, H. Pozidis, A. Walls
US Patent 10,977,181

Calculating corrective read voltage offsets in non-volatile random access memory
N. Papandreou, H. Pozidis, N. Ioannou, R. Pletka, R. Stoica, S. Tomic, T. Fisher, A. Fry
US Patent 10,957,407

Garbage collection in non-volatile memory that fully programs dependent layers in a target block
R. Pletka, N. Papandreou, S. Tomic, N. Ioannou, A. Fry, T. Fisher
US Patent 10,956,317

Wear-aware block mode conversion in non-volatile memory
S. Tomic, R. Pletka, N. Ioannou, N. Papandreou, A. Fry, T. Fisher, R. Stoica
US Patent 10,956,049

Adaptive data and parity placement using compression ratios of storage devices
R. Pletka, S. Tomic, T. Fisher, N. Papandreou, N. Ioannou, A. Fry
US Patent 10,942,808


Managing programming errors in NAND flash memory
N. Papandreou, T. Mittelholzer, R. Pletka
US Patent 10,937,512


Addressing page-correlated read issues using intra-block parity
S. Tomic, N. Papandreou, R. Pletka, N. Ioannou
US Patent 10,929,069


2020


Reducing block calibration overhead using read error triage
S. Tomic, T. Fisher, N. Papandreou, R. Pletka, N. Ioannou, H. Pozidis, A. Fry
US Patent 10,783,024

Updating prefix codes for pseudo-dynamic data compression
C. Camp, H. Pozidis, N. Papandreou, R. Pletka, T. Mittelholzer, T. Parnell, T. Blaettler
US Patent 10,700,702

Adaptive read voltage threshold calibration in non-volatile memory
R. Pletka, N. Papandreou, S. Tomic, N. Ioannou, H. Pozidis, T. Fisher, A. Fry
US Patent 10,699,791

Methods for read threshold voltage shifting in non-volatile memory
N. Ioannou, H. Pozidis, N. Papandreou, R. Pletka, S. Tomic, A. Fry, T. Fisher
US Patent 10,658,054

Mitigating asymmetric transient errors in non-volatile memory by proactive data relocation
R. Pletka, N. Papandreou, S. Tomic, N. Ioannou, A. Fry, T. Fisher
US Patent 10,656,847

Calibration of open blocks in NAND flash memory
N. Papandreou, R. Pletka, S. Tomic, N. Ioannou, H. Pozidis, A. Fry, T. Fisher
US Patent 10,614,881

Background mitigation reads in a non-volatile memory system
N. Papandreou, S. Tomic, R. Pletka, N. Ioannou, H. Pozidis, A. Fry, T. Fisher
US Patent 10,552,063


2019

Reducing read errors by performing mitigation reads to blocks of non-volatile memory
A. Yanes, T. Fisher, C. Keller, J. Ma, K. Sallese, A. Fry, V. Huynh, N. Papandreou
US Patent 10,489,086


Techniques for reducing read voltage threshold calibration in non-volatile memory
M. Reuter, S. Tomic, N. Papandreou, T. Fisher, A. Fry, R. Pletka, N. Ioannou, H. Pozidis
US Patent 10,453,537

Data protection techniques for a non-volatile memory array
T. Fisher, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis, A. Walls
US Patent 10,417,088



State-dependent read voltage threshold adaptation for nonvolatile memory
T. Fisher, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis
US Patent 10,236,067



2018

Estimation of level-thresholds for memory cells
T. Mittelholzer, N. Papandreou, H. Pozidis
US Patent 9,928,923 (First publication: US 2015/0085591 A1)

Workload-adaptive data packing algorithm
C. Camp, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis
US Patent 10,162,700

Mitigating read errors following programming in a multi-level non-volatile memory
C. Camp, T. Fisher, A. Fry, N. Ioannou, T. Mittelholzer, N. Papandreou, T. Parnell, R. Pletka, H. Pozidis, S. Tomic
US Patent 10,101,931

Multi-chip device and method for storing data
T. Blaettler, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis, M. Stanisavljevic
US Patent 10,042,699

Page-level health equalization
C. Camp, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis
US Patent 9,990,279

Reducing read disturb effect on partially programmed blocks of non-volatile memory
C. Camp, T. Fisher, T. Griffin, T. Mittelholzer, N. Papandreou, T. Parnell, R. Pletka, H. Pozidis, G. Tressler, S. Tomic
US Patent 10,115,472


2017

Conditioning phase change memory cells
N. Papandreou, H. Pozidis
US Patent 9,558,817

Data encoding in solid-state storage devices
T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis
US Patent 9,734,012

Data packing for compression-enabled storage systems
C. Camp, T. Fisher, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis
US Patent 9,712,190

Device and method for storing data in a plurality of multi-level cell memory chips
T. Blaettler, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis, M. Stanisavljevic
US Patent 9,672,921

Memory architecture for storing data in a plurality of memory chips
T. Antonakopoulos, N. Papandreou, H. Pozidis
US Patent 9,672,910

Determining a cell state of a resistive memory cell
N. Papandreou, H. Pozidis, M. Stanisavljevic
US Patent 9,666,273

Diagonal anti-diagonal memory structure
T. Blaettler, C. Camp, T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis
US Patent 9,647,694

Device for selecting a level for at least one read voltage
C. Camp, E. Eleftheriou, T. Mittelholzer, T. Parnell, N. Papandreou, H. Pozidis, A. Walls
US Patent 9,639,462

Adapting erase cycle parameters to promote endurance of a memory
T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis, G. Tressler
US Patent 9,588,702

Estimation of level-thresholds for memory cells
T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis, M. Stanisavljevic
US Patent 9,583,184


Extending useful life of a non-volatile memory by health grading
C. Camp, I. Koltsidas, N. Papandreou, T. Parnell, R. Pletka, H. Pozidis, G. Tressler, A. Walls
US Patent 9,558,107


2016

Multi-stage codeword detector
T. Antonakopoulos, T. Mittelholzer, N. Papandreou, H. Pozidis
US Patent 9,477,540 (First publication: US 2015/0149816 A1)

Enhanced temperature compensation for resistive memory cell circuits
N. Papandreou, H. Pozidis, M. Stanisavljevic
US Patent 9,520,189


Dynamically optimizing flash data retention or endurance based on data write frequency
C. Camp, T. Fisher, A. Fry, N. Papandreou, T. Parnell, H. Pozidis, A. Walls
US Patent 9,496,043

Correlation detector
N. Papandreou, A. Sebastian, T. Tuma
US Patent 9,466,364

Data encoding in solid-state storage apparatus
T. Mittelholzer, N. Papandreou, H. Pozidis
GB Patent 2522960

Error-correction encoding and decoding
T. Mittelholzer, N. Papandreou, T. Parnell, H. Pozidis
GB Patent 2525430


Read-detection in multi-level cell memory
T. Mittelholzer, N. Papandreou, H. Pozidis
US Patent 9,305,639


Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
C. Camp, T. Fisher, A. Fry, N. Ioannou, I. Koltsidas, N. Papandreou, T. Parnell, R. Pletka, H. Pozidis, S. Tomic
US Patent 9,251,909


2015

Level-estimation in multi-level cell memory
T. Mittelholzer, N. Papandreou, H. Pozidis
US Patent 9,202,580 (First publication: US 2014/0211564 A1)

Detecting codewords in solid-state storage devices
T. Mittelholzer, N. Papandreou, H. Pozidis
US Patent 8,930,803


Programming of phase-change memory cells
A. Pantazi, N. Papandreou, H. Pozidis, A. Sebastian
US Patent 9,070,438

Read-detection in solid-state storage devices
T. Mittelholzer, N. Papandreou, H. Pozidis
US Patent 8,938,665

Level placement in solid-state memory
N. Papandreou, H. Pozidis
US Patent 9,047,179


2014


Determining cell-state in phase-change memory
U. Frey, A. Pantazi, N. Papandreou, H. Pozidis, A. Sebastian
US Patent 8,755,214


2013

Read/write operations in solid-state storage devices
T. Mittelholzer, N. Papandreou, H. Pozidis
WO/2013/093669

Multilevel programming of phase change memory
E. Eleftheriou, A. Pantazi, N. Papandreou, H. Pozidis, A. Sebastian
US Patent 8,351,251

Programming multi-level phase change memory cells
E. Eleftheriou, A. Pantazi, N. Papandreou, H. Pozidis, A. Sebastian
US Patent 8,441,847



2012

Programming of phase-change memory cells
A. Pantazi, N. Papandreou, H. Pozidis, A. Sebastian, U. Frey
WO/2012/120400

Cell-state determination in phase-change memory
E. Eleftheriou, A. Pantazi, N. Papandreou, H. Pozidis, A. Sebastian
WO/2012/029007


2011

Programming at least one multi-level phase change memory cell
E. Eleftheriou, A. Pantazi, N. Papandreou, H. Pozidis, A. Sebastian
WO/2011/121491




Projects and Groups