Raphael Polig 
contact information
Research Staff MemberZurich Research Laboratory, Zurich, Switzerland +41
447248446
447248446 links
Professional Associations
Professional Associations: IEEE2018
Non-deterministic finite state machine module for use in a regular expression matching system
Kubilay Atasu, Christoph Hagleitner, Raphael Polig, Frederick R Reiss
US Patent 9,983,876
Kubilay Atasu, Christoph Hagleitner, Raphael Polig, Frederick R Reiss
US Patent 9,983,876
2017
Interposer for dynamic mapping of API calls
Giefers, Heiner and Polig, Raphael
US Patent 9,703,573
Abstract
Giefers, Heiner and Polig, Raphael
US Patent 9,703,573
Abstract
Sparse matrix multiplication using a single field programmable gate array module
Bekas, Costas and Curioni, Alessandro and Giefers, Heiner and Hagleitner, Christoph and Polig, Raphael C and Staar, Peter WJ
US Patent 9,558,156
Abstract
Bekas, Costas and Curioni, Alessandro and Giefers, Heiner and Hagleitner, Christoph and Polig, Raphael C and Staar, Peter WJ
US Patent 9,558,156
Abstract
2016
2015
CONJUGATE GRADIENT SOLVERS FOR LINEAR SYSTEMS
Christoph M Angerer, Konstantinos Bekas, Alessandro Curioni, Silvio Dragone, Christoph Hagleitner, Raphael C Polig
US Patent 20,150,293,882
Christoph M Angerer, Konstantinos Bekas, Alessandro Curioni, Silvio Dragone, Christoph Hagleitner, Raphael C Polig
US Patent 20,150,293,882
Iterative refinement apparatus
Christoph M Angerer, Konstantinos Bekas, Alessandro Curioni, Silvio Dragone, Heiner Giefers, Christoph Hagleitner, Raphael C Polig
US Patent App. 14/623,310
Christoph M Angerer, Konstantinos Bekas, Alessandro Curioni, Silvio Dragone, Heiner Giefers, Christoph Hagleitner, Raphael C Polig
US Patent App. 14/623,310
Adaptable and Extensible Runtime and System for Heterogeneous Computer Systems
Christoph M Angerer, Raphael Polig
US Patent App. 14/750,994
Christoph M Angerer, Raphael Polig
US Patent App. 14/750,994
Defective memory column replacement with load isolation
Silke Penth, Raphael Polig, Tobias Werner, Alexander Woerner
US Patent 8,964,493
Silke Penth, Raphael Polig, Tobias Werner, Alexander Woerner
US Patent 8,964,493
2014
Integrated circuit schematics having imbedded scaling information for generating a design instance
Michael Kugel, Stefan Payer, Raphael Polig, Tobias Werner
US Patent 8,918,749
Michael Kugel, Stefan Payer, Raphael Polig, Tobias Werner
US Patent 8,918,749
Method and system for generating a placement layout of a VLSI circuit design
Tobias Werner, Anthony Parent, Raphael Polig, Alexander Woerner
US Patent 8,631,376
Tobias Werner, Anthony Parent, Raphael Polig, Alexander Woerner
US Patent 8,631,376
2011
GLOBAL BIT LINE RESTORE BY MOST SIGNIFICANT BIT OF AN ADDRESS LINE
Michael KUGEL, Raphael POLIG, Tobias T WERNER, others
US Patent App. 13/179,684
Michael KUGEL, Raphael POLIG, Tobias T WERNER, others
US Patent App. 13/179,684
2010
Interleave Memory Array Arrangement
Yuen H Chan, Michael Kugel, Raphael Polig, Tobias Werner
US Patent App. 12/821,064
Yuen H Chan, Michael Kugel, Raphael Polig, Tobias Werner
US Patent App. 12/821,064