Alper Buyuktosunoglu  Alper Buyuktosunoglu photo         

contact information

Principal Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  

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Professional Associations

Professional Associations:  ACM  |  ACM SIGARCH  |  ACM SIGMICRO  |  Fellow, IEEE  |  IEEE


 

  1. Providing a Dynamic Random-Access Memory Cache as Second Type Memory, B. Abali, A. Buyuktosunoglu, B. Sinharoy, number 11,221,770, issued 01/11/2022
  2. Model Training by Discarding Relatively Less Relevant Parameters, P. Bose, A. Buyuktosunoglu, A. Vega, number 11,182,674, issued 11/23/2021
  3. Power Shifting Among Hardware Components in Heterogeneous System, E. Lee, A. Buyuktosunoglu, M. Broyles, T. Rosedahl, number 11,157,067, issued 10/26/2021
  4. Computing with Unreliable Processor Cores, S. Rama, A. Vega, A. Buyuktosunoglu, P. Bose, number 11,151,002, issued 10/19/2021
  5. Dynamically Optimizing Margins of a Processor, P. Lobo, P. Parashurama, T. Webel, R. Bertran, A. Buyuktosunoglu, number 11,150,716, issued 10/19/2021
  6. Generating Representative Microbenchmarks, A. Buyuktosunoglu, R. Bertran, C. Bulla, P. Bose, H. Franke, number 11,074,155, issued 07/27/2021
  7. On-chip Supply Noise Voltage Reduction or Mitigation Using Local Detection Loops, P. Bose, A. Buyuktosunoglu, P. Chuang, P. Restle, C. Vezyrtzis, number 11,073,884, issued 07/27/2021
  8. Microarchitectural Techniques to Mitigate Cache-Based Data Security Vulnerabilities, P. Nair, S. Hong, A. Buyuktosunoglu, R. Nair, number 11,068,612, issued 07/20/2021
  9. Self-Evaluating Array of Memory, A. Buyuktosunoglu, S. Venkataramani, R. Joshi, K. Swaminathan, S. Eldridge, P. Bose, number 11,037,650, issued 06/15/2021
  10. Mitigating Voltage Droop, T. Webel, P. Lobo, A. Buyuktosunoglu, R. Bertran, P. Parashurama, A. Kapoor, number 11,029,742, issued 06/08/2021
  11. Low-Overhead Error Prediction and Preemption in Deep Neural Network Using Apriori Network Statistics, S. Venkataramani, S. Eldridge, K. Swaminathan, A. Buyuktosunoglu, P. Bose, number 11,016,840, issued 05/25/2021
  12. Determination and Correction of Physical Circuit Event Related Errors of a Hardware Design, P. Bose, A. Buyuktosunoglu, S. Eldridge, K. Swaminathan, Y. Zu, number 11,002,791, issued 05/11/2021
  13. Multi-Layered Processor Throttle Controller, P. Lobo, T. Webel, P. Parashurama, A. Buyuktosunoglu, number 10,995,906, issued 03/23/2021
  14. Reliability-Aware Runtime Optimal Processor Configuration, K. Swaminathan, R. Bertran, A. Buyuktosunoglu, P. Bose, N. Chandramoorthy, C. Cher, number 10,896,146, issued 01/19/2021
  15. Cognitive Computing for Servers and Mobile Devices, P. Bose, A. Buyuktosunoglu, A. Vega, number 10,839,311, issued 11/17/2020
  16. Multi-Tag Storage Techniques for Efficient Data Compression in Caches, P. Nair, S. Hong, A. Buyuktosunoglu, M. Healy, B. Abali, number 10,831,669, issued 11/10/2020
  17. Contention-Aware Resource Provisioning in Heterogeneous Processors, N. Chandramoorthy, K. Swaminathan, R. Bertran, A. Buyuktosunoglu, P. Bose, number 10,831,543, issued 11/10/2020
  18. Reducing Minimum Operating Voltage Through Heterogeneous Codes, J. Leng, A. Buyuktosunoglu, P. Bose, R. Bertran, number 10,831,535, issued 11/10/2020
  19. Variation-Aware Intra-Node Power Shifting Among Different Hardware Components, E. Lee, B. Acun, Y. Park, A. Morari, A. Buyuktosunoglu, number 10,761,583, issued 09/01/2020
  20. Determination and Correction of Physical Circuit Event Related Errors of a Hardware Design, P. Bose, A. Buyuktosunoglu, S. Eldridge, K. Swaminathan, Y. Zu, number 10,690,723, issued 06/23/2020
  21. Predicting Voltage Guardband and Operating at a Safe Limit, R. Bertran, P. Bose, A. Buyuktosunoglu, J. Leng, number 10,642,342, issued 05/05/2020
  22. Optimization of Application Workflow in Mobile Embedded Devices, R. Bertran, P. Bose, A. Buyuktosunoglu, C. Cher, H. Jacobson, W. Song, K. Swaminathan, A. Vega, L. Wang, number 10,635,490, issued 04/28/2020
  23. Inducing Heterogeneous Microprocessor Behavior Using Non-Uniform Cooling, P. Bose, A. Buyuktosunoglu, T. Chainer, P. Parida, A. Vega, number 10,613,603, issued 04/07/2020
  24. Self-Evaluating Array of Memory, A. Buyuktosunoglu, S. Venkataramani, R. Joshi, K. Swaminathan, S. Eldridge, P. Bose, number 10,607,715, issued 03/31/2020
  25. Cognitive Computing for Servers and Mobile Devices, P. Bose, A. Buyuktosunoglu, A. Vega, number 10,599,996, issued 03/24/2020
  26. Computer System Performance Analyzer, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 10,599,432, issued 03/24/2020
  27. Adaptive Network with Interconnected Autonomous Devices, A. Buyuktosunoglu, P. Bose, A. Vega, number 10,582,421, issued 03/03/2020
  28. Dynamic Adjustments within Memory Systems, P. Nair, A. Buyuktosunoglu, P. Bose, number 10,558,518, issued 02/11/2020
  29. Sensor Based Non-Uniform Cooling, P. Bose, A. Buyuktosunoglu, T. Chainer, P. Parida, A. Vega, number 10,558,249, issued 02/11/2020
  30. Proactive Voltage Droop Reduction and/or Mitigation in a Processor Core, G. Biran, P. Bose, A. Buyuktosunoglu, P. Chuang, P. Lobo, R. Bertran, P. Restle, C. Vezyrtzis, T. Webel, number 10,552,250, issued 02/04/2020
  31. Local Computation Logic Embedded in a Register File to Accelerate Programs, P. Bose, A. Buyuktosunoglu, J. Derby, M. Franceschini, R. Montoye, A. Vega, number 10,534,608, issued 01/14/2020
  32. Power Shifting in Multicore Platforms by Varying SMT Levels, P. Bose, A. Buyuktosunoglu, H. Franke, P. Tembey, D. Silva, number 10,444,812, issued 10/15/2019
  33. Bandwidth Efficient Techniques for Enabling Tagged Memories, A. Buyuktosunoglu, S. Hong, P. Nair, number 10,423,538, issued 09/24/2019
  34. Adaptive Network with Interconnected Autonomous Devices, A. Buyuktosunoglu, P. Bose, A. Vega, number 10,368,267, issued 07/30/2019
  35. Determination and Correction of Physical Circuit Event Related Errors of a Hardware Design, P. Bose, A. Buyuktosunoglu, S. Eldridge, K. Swaminathan, Y. Zu, number 10,365,327, issued 07/30/2019
  36. Maintaining System Reliability in a CPU with Co-Processors, R. Bertran, P. Bose, A. Buyuktosunoglu, J. Leng, number 10,339,015, issued 07/02/2019
  37. On-Chip Supply Noise Voltage Reduction or Mitigation Using Local Detection Loops in a Processor Core, P. Bose, A. Buyuktosunoglu, P. Chuang, P. Restle, C. Vezyrtzis, number 10,333,520, issued 06/25/2019
  38. Maintaining System Reliability in a CPU with Co-Processors, R. Bertran, P. Bose, A. Buyuktosunoglu, J. Leng, number 10,331,529, issued 06/25/2019
  39. Inducing Heterogeneous Microprocessor Behavior Using Non-Uniform Cooling, P. Bose, A. Buyuktosunoglu, T. Chainer, P. Parida, A. Vega, number 10,317,962, issued 06/11/2019
  40. On-Chip Supply Noise Voltage Reduction or Mitigation Using Local Detection Loops in a Processor Core, P. Bose, A. Buyuktosunoglu, P. Chuang, P. Restle, C. Vezyrtzis, number 10,171,081, issued 01/01/2019
  41. Predicting Voltage Guardband and Operating at a Safe Limit, R. Bertran. P. Bose, A. Buyuktosunoglu, J. Leng, number 10,114,449, issued 10/30/2018
  42. Adaptive Network with Interconnected Autonomous Devices, A. Buyuktosunoglu, P. Bose, A. Vega, number 10,075,875, issued 09/11/2018
  43. Generation and Application of Stressmarks in a Computer System, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 10,042,642, issued 08/07/2018
  44. Clustering Execution in a Processing System to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,933,844, issued 04/03/2018
  45. Clustering Execution in a Processing System to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,921,639, issued 03/20/2018
  46. Space Reduction in Processor Stressmark Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,804,849, issued 10/31/2017
  47. Space Reduction in Processor Stressmark Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,798,546, issued 10/24/2017
  48. Processor with Memory-Embedded Pipeline for Table-Driven Computation, P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,740,497, issued 08/22/2017
  49. Processor with Memory-Embedded Pipeline for Table-Driven Computation, P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,740,496, issued 08/22/2017
  50. Generation and Application of Stressmarks in a Computer System, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,727,434, issued 08/08/2017
  51. Power Shifting in Multicore Platforms by Varying SMT Levels, P. Bose, A.Buyuktosunoglu, H. Franke, P. Tembey, D. Silva, number 9,710,044, issued 07/18/2017
  52. Three-Dimensional Processing System Having at Least One Layer with Circuitry Dedicated to Scan Testing and System State Checkpointing of Other System Layers, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,696,379, issued 07/04/2017
  53. Optimization of Application Workflow in Mobile Embedded Devices, R. Bertran, P. Bose, A. Buyuktosunoglu, C. Cher, H. Jacobson, W. Song, K. Swaminathan, A. Vega, L. Wang, number 9,690,555, issued 06/27/2017
  54. Predicting Out-of-Order Instruction Level Parallelism Of Threads in a Multi-Threaded Processor, I. Burcea, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 9,652,243, issued 05/16/2017
  55. Intelligent Bandwidth Shifting Mechanism, P. Bose, A. Buyuktosunoglu, V. Jimenez, F. O'Connell, number 9,645,935, issued 05/09/2017
  56. Delaying Execution in a Processor to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,632,560, issued 04/25/2017
  57. Delaying Execution in a Processor to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,632,559, issued 04/25/2017
  58. Single-Thread Cache Miss Rate Estimation, J. Bonanno, A. Buyuktosunoglu, B. Curran, W. Hinrichs, C. Jacobi, B. Prasky, M. Recktenwald, A. Saporito, V. Srinivasan, J. Wellman, number  9,626,293, issued 04/18/2017
  59. Single-Thread Cache Miss Rate Estimation, J. Bonanno, A. Buyuktosunoglu, B. Curran, W. Hinrichs, C. Jacobi, B. Prasky, M. Recktenwald, A. Saporito, V. Srinivasan, J. Wellman, number  9,619,385, issued 04/11/2017
  60. Idle-Aware Margin Adaption, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,618,999, issued 04/11/2017
  61. Generation and Application of Stressmarks in a Computer System, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,588,863, issued 03/07/2017
  62. Processor Stressmarks Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, number 9,575,868, issued 02/21/2017
  63. Processor Stressmarks Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, number 9,575,867, issued 02/21/2017
  64. 3-D Stacked Multiprocessor Structure with Vertically Aligned Identical Layout Operating Processors in Independent Mode or in Sharing Mode Running Faster Components, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,569,402, issued 02/14/2017
  65. Cycle-Level Thread Alignment on Multi-Threaded Processors, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,507,646, issued 11/29/2016
  66. Multi-Threaded Processor Instruction Balancing Through Instruction Uncertainty, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 2513787(UK), issued 11/23/2016 (also issued as ZL201380008222.1 on 10/05/2016)
  67. 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,471,535, issued 10/18/2016 (also issued as ZL201310137022.8 on 12/28/2016)
  68. Predictively Turning Off a Charge Pump Supplying Voltage for Overdriving Gates of the Power Switch Header in a Microprocessor with Power Gating, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,471,136, issued 10/18/2016
  69. 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,442,884, issued 09/13/2016
  70. Determining and Storing Bit Error Rate Relationships in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,431,084, issued 08/30/2016
  71. Hierarchical In-Memory Sort Engine, A. Buyuktosunoglu, S. Chellappa, T. Kirihata, K. Swaminathan, number 9,424,308, issued 08/23/2016
  72. Accelerating Microprocessor Core Wake Up via Charge from Capacitance Tank Without Introducing Noise on Power Grid of Running Microprocessor Cores, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,423,865, issued 08/23/2016
  73. Delaying Execution in a Processor to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,423,859, issued 08/23/2016
  74. Determining and Storing Bit Error Rate Relationships in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,418,721, issued 08/16/2016
  75. Dynamic Temperature Adjustments in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,406,368, issued 08/02/2016
  76. Hierarchical In-Memory Sort Engine, A. Buyuktosunoglu, S. Chellappa, T. Kirihata, K. Swaminathan, number 9,396,143, issued 07/19/2016
  77. Three-Dimensional Processing System Having Independent Calibration and Statistical Collection Layer, A. Buyuktosunoglu, P.Emma, A. Hartstein, M. Healy, K. Kailas, number 9,389,876, issued 07/12/2016
  78. Power Management for In-Memory Computer Systems, P. Bose, A. Buyuktosunoglu, B. Fleischer, T. Fox, H. Jacobson, R. Nair, A. Vega, number 9,389,675, issued 07/12/2016
  79. Predictively Turning Off a Charge Pump Supplying Voltage for Overdriving Gates of the Power Switch Header in a Microprocessor with Power Gating, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,389,674, issued 07/12/2016
  80. Three-Dimensional Processing System Having at Least One Layer with Circuitry Dedicated to Scan Testing and System State Checkpointing of Other System Layers, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,383,411, issued 07/05/2016
  81. Dynamic Power Distribution, P. Bose, A. Buyuktosunoglu, H. Jacobson, number 9,372,519, issued 06/21/2016
  82. Dynamic Detection of Resource Management Anomalies in a Processing System, P. Bose, A. Buyuktosunoglu, A. Vega, number 9,361,175, issued 06/07/2016
  83. Power Management for Multi-Core Processing Systems, P. Bose, A. Buyuktosunoglu, M. Floyd, H. Hanson, H. Jacobson, K. Rajamani, S. Ramani, T. Rosedahl, A. Vega, number 9,354,943, issued 05/31/2016
  84. Dynamic Temperature Adjustments in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,351,899, issued 05/31/2016
  85. Three-Dimensional Processing System Having Multiple Caches That Can Be Partitioned, Conjoined, and Managed According to More Than One Set of Rules and/or Configurations, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,336,144, issued 05/10/2016
  86. Rotating Voltage Control, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,323,302, issued 04/26/2016
  87. 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number ZL201310137331.5, issued 03/30/2016
  88. Dynamic Power Distribution, P. Bose, A. Buyuktosunoglu, H. Jacobson, number 9,298,234, issued 03/29/2016
  89. Accelerating the Microprocessor Core Wakeup by Predictively Executing a Subset of the Power-Up Sequence, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,298,253, issued 03/29/2016
  90. 3-D Stacked Multiprocessor Structure with Vertically Aligned Identical Layout Operating Processors in Independent Mode or in Sharing Mode Running Faster Components, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,298,672, issued 03/29/2016
  91. Multi-Threaded Processor Instruction Balancing Through Instruction Uncertainty, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 9,298,466, issued 03/29/2016
  92. Accelerating the Microprocessor Core Wakeup by Predictively Executing a Subset of the Power-Up Sequence, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,292,079, issued 03/22/2016
  93. Hierarchical In-Memory Sort Engine, A. Buyuktosunoglu, S. Chellappa, T. Kirihata, K. Swaminathan, number 9,268,863, issued 02/23/2016
  94. Memory Architectures Having Wiring Structures that Enable Different Access Patterns in Multiple Dimensions, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,257,152, issued 02/09/2016
  95. Three-Dimensional Computer Processor Systems Having Multiple Local Power and Cooling Layers and A Global Interconnection Structure, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, M. Scheuermann, number 9,195,630, issued 11/24/2015
  96. Memory Architectures Having Wiring Structures that Enable Different Access Patterns in Multiple Dimensions, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,190,118, issued 11/17/2015
  97. Multi-Threaded Processor Instruction Balancing Through Instruction Uncertainty, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 9,182,991, issued 11/10/2015
  98. Thread Consolidation in Processor Cores, P. Bose, A. Buyuktosunoglu, B. Rosenburg, K. Ryu, A. Vega, number 9,146,609, issued 9/29/2015
  99. Thread Consolidation in Processor Cores, P. Bose, A. Buyuktosunoglu, B. Rosenburg, K. Ryu, A. Vega, number 9,141,173, issued 9/22/2015
  100. Power Shifting in Multicore Platforms by Varying SMT Levels, P. Bose, A. Buyuktosunoglu, D. Silva, H. Franke, P. Tembey, number 9,043,626, issued 5/26/2015
  101. Power Shifting in Multicore Platforms by Varying SMT Levels, P. Bose, A. Buyuktosunoglu, D. Silva, H. Franke, P. Tembey, number 9,003,218, issued 4/7/2015
  102. Adaptive Workload Based Optimizations Coupled with a Heterogeneous Current-Aware Baseline Design to Mitigate Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,914,764, issued 12/16/2014
  103. Current-Aware Floorplanning to Overcome Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,863,068, issued 10/14/2014
  104. Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,826,216, issued 9/2/2014
  105. 3-D Stacked Multiprocessor Structures and Methods to Enable Reliable Operation of Processors at Speeds above Specified Limits, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 8,826,073, issued 9/2/2014
  106. 3-D Stacked Multiprocessor Structures and Methods to Enable Reliable Operation of Processors at Speeds above Specified Limits, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 8,799,710, issued 8/5/2014
  107. Virtualized Abstraction with Built-in Data Alignment and Simultaneous Event Monitoring in Performance Counter Based Application Characterization and Tuning, P. Bose, A. Buyuktosunoglu, C. Isci, J. Kephart, X. Meng, R. Sarikaya, number 8,798,962, issued 8/5/2014
  108. A Method and System for Computing a Single Thread Performance in a Simultaneous Multithreading Environment, J. Bartik, A. Buyuktosunoglu, B. Curran, C. Jacobi, B. Prasky, J. Wellman, V. Srinivasan, number IPCOM000237737D, published 7/8/2014
  109. An Apparatus for Regulating Voltage by Using Header Devices with Variable Gate Voltage, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number IPCOM000237598D, published 6/26/2014
  110. Apparatus to Provide Multiple Virtual Supply Voltage Points Through Selective Activation of Header Devices, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number IPCOM000237597D, published 6/26/2014
  111. Adaptive Workload Based Optimizations to Mitigate Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,683,418, issued 3/25/2014
  112. On-Chip Power Proxy Based Architecture, P. Bose, A. Buyuktosunoglu, M. Floyd, M. Pesantez, number 8,650,413, issued 2/11/2014
  113. Method and System for Controlling Power in a Chip through a Power-Performance Monitor and Control Unit, P. Bose, A. Buyuktosunoglu, C. Cher, P. Kudva, number 8,639,955, issued 1/28/2014
  114. Dynamically Tune Power Proxy Architectures, E. Acar, P. Bose, B. Brock, A. Buyuktosunoglu, M. Floyd, M. Pesantez, G. Still, number 8,635,483, issued 1/21/2014
  115. Voltage Regulator Module with Power Gating and Bypass, P. Bose, A. Buyuktosunoglu, H. Jacobson, S. Kim, number 8,564,262, issued 10/22/2013
  116. Guarded, Multi-Metric Resource Control for Safe and Efficient Microprocessor Management, P. Bose, A. Buyuktosunoglu, N. Madan, number 8,527,994, issued 9/3/2013
  117. Measuring Data Switching Activity in a Microprocessor, P. Bose, A. Buyuktosunoglu, C. Gonzalez, M. Qureshi, V. Zyuban, number 8,458,501, issued 6/4/2013
  118. Systems and Methods for Thread Assignment and Core Turn-Off for Integrated Circuit Energy Efficiency and High Performance, P. Bose, A. Buyuktosunoglu, E. Kursun, number 8,296,773, issued 10/23/2012
  119. On-Chip Power Proxy Based Architecture, P. Bose, A. Buyuktosunoglu, M. Floyd, number 8,271,809, issued 9/18/2012
  120. Managing Instructions for More Efficient Load/Store Unit Usage, P. Bose, A. Buyuktosunoglu, M. Floyd, D. Nguyen, B. Ronchetti, number 8,271,765, issued 9/18/2012
  121. Power Efficient Thread Priority Enablement, P. Bose, A. Buyuktosunoglu, R. Eickemeyer, S. Eisen, M. Floyd, H. Jacobson, J. Summers, number 8,261,276, issued 9/4/2012
  122. Predictive Power Gating with Optional Guard Mechanism, J. Basak, P. Bose, A. Buyuktosunoglu, A. Lungu, number 8,219,834, issued 7/10/2012
  123. Two-Level Guarded Predictive Power Gating, J. Basak, P. Bose, A. Buyuktosunoglu, A. Lungu, number 8,219,833, issued 7/10/2012
  124. System of Programmable Mode Control within an Instruction Sequencing Unit for Management of Power within a Microprocessor, P. Bose, A. Buyuktosunoglu, M. Floyd, T. Venton, V. Zyuban, number IPCOM000217762D, published 5/11/2012
  125. Adaptive Data Prefetch System and Method, P. Bose, A. Buyuktosunoglu, M. Dooley, M. Floyd, D. Ray, B. Ronchetti, number 8,156,287, issued 4/10/2012
  126. Method and System for Controlling Power in a Chip through a Power-Performance Monitor and Control Unit, P. Bose, A. Buyuktosunoglu, C. Cher, P. Kudva, number 8,112,642, issued 2/7/2012
  127. Self-Tuning Power Management Techniques, R. Bergamaschi, A. Buyuktosunoglu, G. Dittmann, I. Nair, number 8,001,405, issued 8/16/2011
  128. Method and System of Multi-Core Microprocessor Power Management and Control via Per-Chiplet, Programmable Power Modes, P. Bose, A. Buyuktosunoglu, M. Floyd, number 8,001,394, issued 8/16/2011
  129. Method and System of Peak Power Enforcement via Autonomous Token-based Control and Management, P. Bose, A. Buyuktosunoglu, C. Cher, Z. Hu, H. Jacobson, P. Kudva, V. Srinivasan, V. Zyuban, number 7,930,578, issued 4/19/2011
  130. Integrated Co-optimized Adaptive On-chip Power Management Techniques for Multi-Core Systems, R. Bergamaschi, P. Bose, A. Buyuktosunoglu, J. Darringer, G. Dittmann, M. Floyd, I. Nair, number IPCOM000204964D, published 3/14/2011
  131. Dynamic Reconfigurable Memory Hierarchy, D. Albonesi, R. Balasubramonian, A. Buyuktosunoglu, S. Dwarkadas, number 6,684,298, issued 1/27/2004 (reissued as RE42,213 on 3/8/2011)
  132. Adaptive Issue Queue for Reduced Power at High Performance, A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, D. Albonesi, number 7,865,747, issued 1/4/2011
  133. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, D. Albonesi, R. Balasubramonian, A. Buyuktosunoglu, S. Dwarkadas, number 6,834,328, issued 12/21/2004 (reissued as RE41,958 on 11/23/2010)
  134. System and Method for Predicting Hardware and/or Software Metrics in a Computer System Using Models, A. Buyuktosunoglu, R. Sarikaya, number 7,698,249, issued 4/13/2010
  135. Method and Apparatus for Conserving Power by Throttling Instruction Fetching when a Processor Encounters Low Confidence Branches in an Information Handling System, P. Bose, A. Buyuktosunoglu, C. Cher, M. Gschwind, R. Nair, R. Philhower, W. Sauer, R. Yeung, number 7,627,742, issued 12/1/2009 (also issued as ZL200880011619.5 on 10/12/2011, also issued as 1159407 on 6/18/2012, also issued as 5172942 on 1/11/2013)
  136. Methods for Thermal Management of Three-Dimensional Integrated Circuits, P. Bose, A. Buyuktosunoglu, E. Kursun, number 7,487,012, issued 2/3/2009
  137. Cost-Conscious Pre-Emptive Cache Line Displacement and Relocation Mechanisms, A. Buyuktosunoglu, Z. Hu, J. Rivers, J. Robinson, X. Shen, V. Srinivasan, number 7,454,573, issued 11/18/2008
  138. Arrangements for Reducing Latency and Snooping Cost in Non-Uniform Cache Memory Architectures, A. Buyuktosunoglu, Z. Hu, J. Rivers, J. Robinson, X. Shen, V. Srinivasan, number CN ZL200610005935.4, issued 11/5/2008
  139. Systems and Methods for Mutually Exclusive Activation of Microprocessor Resources to Control Maximum Power, P. Bose, A. Buyuktosunoglu, Z. Hu, H. Jacobson, V. Srinivasan, V. Zyuban, number 7,447,923, issued 11/4/2008 (also issued as ZL200680030136.0 on 5/4/2011, as 4811879 on 9/2/2011)
  140. Method and System for Controlling Power in a Chip through a Power-Performance Monitor and Control Unit, P. Bose, A. Buyuktosunoglu, C. Cher, P. Kudva, number 7,421,601, issued 9/02/2008
  141. Adaptive Fetch Gating in Multithreaded Processors, Fetch Control and Method of Controlling Fetches, P. Bose, A. Buyuktosunoglu, R. Eickemeyer, L. Eisen, P. Emma, J. Griswell, Z. Hu, H. Le, D. Logan, B. Sinharoy, number 7,392,366, issued 6/24/2008
  142. Apparatus and Method for Dynamic Control of Double Gate Devices, A. Buyuktosunoglu, O. Dokumaci, number 7,170,772, issued 1/30/2007
  143. Method and Structure for Short Range Leakage Control in Pipelined Circuits, H. Jacobson, P. Bose, A. Buyuktosunoglu, P. Cook, P. Emma, P. Kudva, S. Schuster,number 6,946,869, issued 9/20/2005