Key to Global Clock Network Visualizations
This page contains detailed explanation of the global clock visualizations contained in the next page
The visualizations on the "Clock Network Visualization" page use X,Y just like the actual layout. So viewed "from above" (i.e. looking down from a big Z value) they look like a regular layout (see Fig 3 a,b below), except that the wire widths are distorted and colored funny.
In both visualizations, the "Z axis" of pictures has nothing to do with the real Z axis (perpendicular surface) of the real chip. Fortunately since the long wires are all on the top 2 layers of metal, there is not much info in the real Z coordinate info anyway, so we just ignore it away and replace it with something more fun.
In Fig. 1, I used the Z axis to represent "clock latency" i.e. how long it took for a clock edge to travel from the PLL to each end of every wire segment and buffer. In that picture the wire widths were actually proportional to the physical wire widths, just exaggerated for visibility, and turned into hollow circular "tubes". The colors also come from the delay to that point in each wire. The buffers were also displayed, all with the same width, and they appear as "vertical tubes" because both ends (input and output) have almost the same X,Y coordinate, but the delay of the buffer (Z coordinates) are significantly different:
Fig 1: Both Z and Color to represent Time (or Delay), and diameter represents wire width for wires, and nothing for buffers (all the same). Note, since delay is monotonically increasing, the tree grows monotonically "up" unless some element has negative delay. I’ve also added yellow spheres, whose diameter represents the local load density (I do not visualize individual loads, that are too numerous to visualize).
Next lets discuss the animations, one frame of which is shown here:
Fig 2: Here Z represent Voltage, and the diameter and color represents current for both wire segments and buffers, and a snapshot was taken every 5 ps, for a total of 3 cycles (200 ps). 600 ps is roughly the clock latency + 1 more cycle.
On POWER6, the clock-edge voltage "wave" takes about 1.8 cycles to travel all the way the clock distribution, so the voltage at the PLL at the center rises to Vdd (increasing Z) and drops back down to Gnd twice by the time the little piece of grid shown at the right edge finally switches up to Vdd the first time.
Color: The wires and buffers remain a cool blue color until current starts traveling through them. In the PowerSpice simulations, Mike Thomson put a current meter at each end of every wires and buffer to measure the current at both ends, i.e. the input and output of every buffer and wire.
The yellow wire-frame box shows both Vdd and Gnd. Notice that there are many nodes that over and undershoot significantly. We carefully kept track of this over/undershoot in case of oxide reliability concerns, although after discussion with oxide reliability guys, we realized that Vcs is probably a much bigger concern than our clock distribution overshoots.
If I rotate a couple frames of the Voltage Current to look down from the top above, we can't see the voltages, just the currents:
Fig 3 (a) t=0 (b) t=360 (sector buffers and wires switching hard)
Fig 3 a,b: At t=0 there are no currents, but at t=360 ps, there are some big currents at the sector buffers in the small piece of core mesh visualized. It is clear here that I included only a "cross-section" of the "L1" distribution including only 6 of the 88 sector buffers in the top core (and none in the bottom core). When I tried to include all the wires, CPU time to make the movies was much longer, and the results were less understandable.
The Clocktree & PowerSpice simulation time for this was 4 CPU minutes, and the visualizations took a similar time, with another few minutes to convert to miff files to animated gifs. The Voltage/Current cross-section animation shows about 5000 wire segments. The delay picture shows about 20,000 wires.
Looking carefully at certain frames, you can see more current & voltage details:
Fig. 4) Note the buffer at the top of the picture above (the short cone pointing up): Because the current going into the input (top) of the buffer is small, the cone is small at the top/input, but the current coming out of the bottom/output is large. The pink->red colors show the largest currents, most notable in various driver outputs as well as wires driving large loads. In the picture above, the current from the driver then enters into a couple wires, where the current is large near driver but at this moment still small at the far ends, which have barely started to switch "up" from Gnd towards Vdd.
Here's another interesting feature that you would never see without transmission-line models:
Fig 5) Notice the 4 long wires "curling up" as they approach Vdd. The 4 wires are being driven by the two driver "cones" at the top. The far end of the wires has already switched "up" to higher voltages than the middle (driven) parts of the wires due to the reflection from the unterminated far end of these 4 transmission lines. This would never happen with just RC wire models.
Zooming in on the sector buffers at 340 ps:
Fig 6) At this time snapshot, The inputs to the 6 sector buffers shown (2 are almost obscured) have finally switched up almost to Vdd, but since our sector buffers are 3 inverters in series they have significant delay, so that the output of these 6 sector buffers are near Gnd, and have not started switching yet. All the other buffers are single inverters, except for the 2-stage programmable delay buffers).
All this represents real PowerSpice simulation results except for one thing: I must admit to one bit of "artistic license": In real life, all our buffers are inverting buffers (except for the prog_dly_macprogrammable delay buffer). Thus at t=0, instead of a simple "flat" picture with everything at V=0, we really have this:
Fig 7) This shows that the buffer inputs and outputs have "opposite" phase. When animated, this is interesting, but very hard to understand and explain, so I took some liberty and post-processed the voltages as follows. All node voltages are either 0 or Vdd at t=0 as shown here. If at t=0 a node was at Vdd, then I replaced V(t) with Vdd-V(t) for all times, effectively removing inversions.
I hope you ejoyed these visualizations. They are not just pretty, we occasionally use them to understand unexpected simulation results of real designs. The kind of "intuitive" understanding engendered by studying such visulizations, can often help lead to problem solutions, better designs, and better designers.