Jaime H Moreno 
contact information
Distinguished ResearcherThomas J. Watson Research Center, Yorktown Heights, NY USA +1
9149454340
9149454340 links
Professional Associations
Professional Associations: ACM | ACM Distinguished Speaker | ACM SIGARCH | ACM SIGMICRO | IEEE | IEEE Computer Society- Active memory device gather, scatter, and filter
US Patent 10,049,061 (B. Fleischer, T. Fox, H. Jacobson, J.A. Kahle, J.H. Moreno, R. Nair), August 2018 - Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry
US Patent 9,632,778 (B. Fleischer, T. Fox, H. Jacobson, J.H. Moreno, R. Nair, D.A. Prener), April 2017 - Tree traversal in a memory device
US Patent 9,064,030 (J. Kahle, J.H. Moreno, R. Nair), June 2015 - Active Buffered Memory
US Patent 9,003,160 (B. Fleischer, T. Fox, H. Jacobson, J. Kahle, J.H. Moreno, R. Nair), April 2015 - Cache line replacement techniques allowing choice of LFU or MFU cache line replacement
US Patent 7,870,341 (R. Matick, J.H. Moreno, M. Ware), January 2011
- Cache with selective least frequently used or most frequently used cache line replacement
US Patent 7,133,971 (R. Matick, J.H. Moreno, M. Ware), November 2006 - System and method for instruction memory storage and processing based on backwards branch control information
US Patent 7,130,963 (S. Asaad, J.H. Moreno, J. Rivers, J.D. Wellman), October 2006 - Selective bypassing of a multi-port register file
US Patent 7,051,186 (V. Zyuban, J.H. Moreno, S. Asaad ), June 2006 - Apparatus and method for updating pointers for indirect and parallel register access
US Patent 7,017,028 (J.H. Moreno, J. Derby, T. Fox, U. Shvadron, F. Neeser, A. Zaks, S.H. Ben-David), March 2006 - Viterbi decoding for SIMD vector processors with indirect vector element access
US Patent 6,954,841 (J.H. Moreno, F. Neeser), October 2005 - Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width
US Patent 6,948,051 (J. Rivers, J.H. Moreno, V. Cuppu), September 2005 - SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath
US Patent 6,915,411 (J.H. Moreno, J. Derby, U. Shvadron, F. Neeser, V. Zyuban, A. Zaks, S.H. Ben-David), July 2005 - System and method for VLSI visualization
US Patent 6,895,372 (S.H. Voldman, P.N. Sanda, D.R. Knebel, M.A. Lavin, S. Polonsky, J.H. Moreno), June 2005 - Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching
US Patent 6,711,651 (J.H. Moreno, J. Rivers, J.D. Wellman), March 2004 - Method and apparatus for reducing encoding needs and ports to shared resources in a processor
US Patent 6,704,855 (J.H. Moreno, M. Moudgill, E. Altman), March 2004 - Method and apparatus for memory prefetching based on intra-page usage history
US Patent 6,678,795 (J. Rivers, J.H. Moreno, J.D. Wellman), January 2004 - Object-code compatible representation of VLIW programs
US Patent 5,951,674 (J.H. Moreno), September 1999 - Apparatus for region-based detection of interference among reordered memory operations
US Patent 5,918,005 (J.H. Moreno, M. Moudgill), June 1999 - Branch on cache hit/miss for compiler assisted miss delay tolerance
US Patent 5,761,515 (P. Dubey, J.H. Moreno, C. Barton), June 1998 - Method and apparatus for reordering memory instructions in a processor
US Patent 5,758,051 (M. Moudgill, J.H. Moreno), May 1998 - Object-code compatible representation of very long instruction word programs
US Patent 5,669,001 (J.H. Moreno), September 1997 - Method and apparatus for reordering memory operations in a superscalar or VLIW processor
US Patent 5,625,835 (J.H. Moreno, K. Ebcioglu, G. Silberman, D. Luick, P. Winterfield), April 1997
Projects and Groups
- 3D VLSI Integration
- Advanced Compiler Technologies
- Blue Gene Watson
- Blue Gene/Q Supercomputer Design
- Computer Architecture
- eLite DSP Project
- Future POWER Systems
- Low Power Processor Microarchitectures
- Main Memory Power, Performance, and Reliability Research
- Microarchitecture Exploration Toolset (MET)
- Power Reduction in High-Performance Microprocessors
- POWER7 (TM) Microprocessor Design
- Reliability and Power-Aware Microarchitectures
- Systems Technology and Microarchitecture
- The Cell Project
- VLIW Architecture
- WSC Cluster