Jaime H Moreno           

2019

• Supercomputer Benchmarks Modeling and Projections, Summit and Sierra Supercomputers from Proposal to Acceptance, Workshop on Modeling and Simulation of Systems and Applications, Seattle, August 2019.
  
  
• Summit and Sierra: The New AI/HPC Supercomputers, International Supercomputer Conference in Mexico, Monterrey, Mexico, March 2019. (http://www.isum.mx/)
  

• Summit and Sierra: The New AI/HPC Supercomputers, Penn State University High-Performance Symposium, Penn State, February 2019
  

2018

• Summit and Sierra: The New AI/HPC Supercomputers, IBM Tokyo Research Center, Tokyo, Japan, November 2018.

2017

• Cognitive Computing and Supercomputing - Convergence and Opportunities, Congress of the Future, Santiago, Chile, February 2017. (https://congresofuturo.senado.cl/)

• Trends and Directions in Data Centric Systems: Cognitive Supercomputers, High-Performance Computing Workshop, Bogota, Colombia, September 2017.

2016

• Cognitive Computing: Evolution in IT Infrastructure, THINK IN Event in the Cognitive Era, IBM Colombia, June 2016.
• Cognitive Computing: Evolution in IT Infrastructure, IBM LatinAmerica event, Panama, April 2016.

• Big Data and Cognitive Computing, Congress of the Future, Santiago, Chile, February 2016
  (https://congresofuturo.senado.cl/)

2015

• Big Data, Analytics, Cognitive: Computational Trends and Challenges, Universidad de Concepción, Concepción, Chile, October 2015.
• Analytics Kernels and Accelerators: Why, What, and Research Directions, Cátedra Universidad Autónoma de Madrid (UAM) - IBM, Madrid, Spain, July 2015.
• Disruptive Infrastructure Innovation on the Cutting Edge of the Cloud, IBM Colombia, Bogotá, Colombia, June 2015.
• Innovations on the cutting edge of cloud, GBM Business Transformation, Cancun, Mexico, May 2015.

2014

• Big Data, Analytics, Data Centric Systems, Cognitive: Computational Trends and Challenges, Cognitive Computer Science Symposium, Cátedra Universidad Autónoma de Madrid (UAM) - IBM, Madrid, Spain, November 2014.
• Big Data and Analytics: Computational Trends and Challenges, Applied Statistics Association Distinguished Seminar, Baruch College, New York, April 2014
• Augmenting Memory Capabilities for Exascale Systems, NNSA ASC Conference, February 2014.

2013

• Computing in High-Performance Systems: Trends and Challenges, Cátedra Universidad Autónoma de Madrid (UAM) - IBM, Madrid, Spain, October 2013.
• Computing in High-Performance Systems: Trends and Challenges, International Symposium NLHPC 2013, Santiago, Chile, October 2013.

2012

• Advanced Memory Concepts, Extreme Scale Research Principal Investigators Meeting, Washington DC, October 2012.

2011

• Trends and Challenges in Performance of Systems and Microprocessors, IBM Industry Solutions Lab, December 2011.
• Workload Optimized Systems, IBM Industry Solutions Lab, May 2011.
• Extreme Scale Computing: Panelist’s View, Panel at High-Performance Computer Architecture Conference, Bangalore, India, January 2011.

2010

• Global Technology Outlook: Information Technology Evolution, IBM Spain University Day, Barcelona, Spain, December 2010.
• Architecture Implications of 3DVLSI on High-End Systems, GSRC Mid-Year Study, May 2010.
• Hybrid Systems, IBM Industry Solutions Lab, May 2010.
• Trends and Challenges for High-End and Exascale Computer Systems, Distinguished Lecture Series, Women in Computing, University of Toronto, Canada, April 2010.

2009

• Hybrid Systems: Systems for the Smart Planet Era, Engineering Students Conference, Veracruz, Mexico, October 2009.
• Technology Outlook and Associated Modeling Challenges for Future Systems, Software-Integrated Multi-Core Modeling Tutorial - ASPLOS, Washington DC, March 2009.
• Transformational Hybrid Systems, IEEE Region I Southern Area Industry Day, Piscataway, February 2009. (http://www.ewh.ieee.org/r1/princeton-centraljersey/abstracts.html#moreno)

2008

• Impact of Technology Trends on Computer Architecture, CRA-W Computer Architecture Summer School on Parallel Programming and Architectures, Providence, August 2008.

2006

• Heterogeneous Parallelism in the Cell Broadband Engine Architecture, Society of Hispanic Professional Engineers, Chicago, November 2006.
• Chip-level integration: the new frontier for microprocessor architecture, Symposium on Parallel Algorithms and Architectures, Boston, August 2006.
• What should Computer Architects know about circuits?, Computer Research Association - Women (CRAW) Computer Architecture Summer Workshop, Princeton, July 2006.
• Compiler Support for Heterogeneous Parallelism in the Cell Broadband Engine Architecture (CBEA), Georgia Tech University, April 2006.

2005

• Innovation and Technology Trends, Keynote Speaker, 10th National Conference on Electronics and Information Technologies (CANIETI), Puerto Vallarta, Mexico, July 2005.
• Innovation and the Future of Technology, IBM On-demand Business Day, Caracas, Venezuela, October 2005.
• Global Technology Outlook 2005, Society of Hispanic Professional Engineers, November 2005.

2004

• Chip-level integration tradeoffs: the new frontier for microprocessor design, Workshop on Compiler and Architectures, IBM Haifa Research Laboratory, December 2004
• Computer Architecture and Software Interactions - Outlook for the Future, Panel at Workshop on Compiler and Architectures, IBM Haifa Research Laboratory, December 2004.
• Chip-level integration tradeoffs: the new frontier for microprocessor design, University of Michigan, May 2004.
• Multithreaded processors, United States Patent Office Training Program, April 2004.

2003

• Challenges in the evolution of server-class instruction-set architectures, Distinguished Seminar Series, Georgia Tech University, November 2003.
• Challenges in the evolution of server-class instruction-set architectures, IBM Research Day, University of Illinois Urbana Champain, September 2003.

2000

• Towards a world of interconnected appliances, Keynote Speaker, Industry Affiliates Program Meeting, University of Puerto Rico Mayaguez, May 2000.
•  

1999

• Modeling and analysis of cache memory hierarchies on server systems, University of California Los Angeles, August 1999.

1998

• An approach for quantifying the impact of not simulating mispredicted paths, Workshop on Performance Analysis and its Impact on Design (PAID), September 1998.
• Trace-driven performance exploration of a PowerPC 601 OLTP workload on wide superscalar processors, Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW'98), February 1998.

1997

• Exploiting instruction-level parallelism through tree-instructions, University of California Los Angeles, October 1997.

1994

• From Scalar to Superscalar to VLIW: An Emerging Technology in Microprocessors, Keynote Speaker, XIV International Conference of the Chilean Computer Society, November 1994.