Amlan Majumdar  Amlan Majumdar photo         

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Research Staff Member
T. J. Watson Research Center, Yorktown Heights, NY, USA
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Professional Associations

Professional Associations:  IEEE


PUBLICATIONS IN JOURNALS

  1. A. Majumdar, “Electron drift velocity versus electric field in III-V semiconductors”, Solid State Electronics, vol. 39, no. 8, pp. 1251-1252, Aug. 1996.
  2. A. Majumdar, “Effect of intrinsic spin on electronic transport through magnetic barriers”, Physical Review B, vol. 54, no. 17, pp. 11911-11913, Nov. 1996. CITATIONS: 76.
  3. A. Majumdar, S. Balasubramanian, V. Venkataraman, and N. Balasubramanian, “Reactivation kinetics of boron acceptors in hydrogenated silicon during zero bias anneal”, Journal of Applied Physics, vol. 82, no. 1, pp. 192-195, Jul. 1997.
  4. A. Majumdar, “A complete charge control model for HEMTs”, Solid State Electronics, vol. 41, no. 11, pp. 1825-1826, Nov. 1997.
  5. A. Majumdar, “Spin polarization and enhancement of the g-factor of one-dimensional electron systems with an in-plane magnetic field”, Journal of Applied Physics, vol. 83, no. 1, pp. 297-301, Jan. 1998.
  6. A. Majumdar, L. P. Rokhinson, D. C. Tsui, L. N. Pfeiffer, and K. W. West, “Effective mass enhancement of two-dimensional electrons in a one-dimensional superlattice potential”, Applied Physics Letters, vol. 76, no. 24, pp. 3600-3602, Jun. 2000. Selected by Virtual Journal of Nanoscale Science & Technology, vol. 1, no. 23, Jun. 2000. CITATIONS: 24.
  7. A. Majumdar, K. K. Choi, L. P. Rokhinson, and D. C. Tsui, “Towards a voltage tunable two-color quantum-well infrared photodetector”, Applied Physics Letters, vol. 80, no. 4, pp. 538-540, Jan. 2002. Selected by Virtual Journal of Nanoscale Science & Technology, vol. 5, no. 5, Feb. 2002.
  8. A. Majumdar, K. K. Choi, J. L. Reno, L. P. Rokhinson, and D. C. Tsui, “A two-color quantum-well infrared photodetector with voltage tunable peaks”, Applied Physics Letters, vol. 80, no. 5, pp. 707-709, Feb. 2002. CITATIONS: 30.
  9. J. Mao, A. Majumdar, K. K. Choi, D. C. Tsui, K. M. Leung, C. H. Lin, T. Tamir, and G. A. Vawter, “Light coupling mechanism of quantum-grid infrared photodetectors”, Applied Physics Letters, vol. 80, no. 5, pp. 868-870, Feb. 2002. Selected by Virtual Journal of Nanoscale Science & Technology, vol. 5, no. 6, Feb. 2002.
  10. A. Majumdar, K. K. Choi, L. P. Rokhinson, J. L. Reno, and D. C. Tsui, “Electron transfer in voltage tunable two-color infrared photodetectors”, Journal of Applied Physics, vol. 91, no. 7, pp. 4623-4630, Apr. 2002. Selected by Virtual Journal of Nanoscale Science & Technology, vol. 5, no. 14, Apr. 2002.
  11. A. Majumdar, K. K. Choi, J. L. Reno, L. P. Rokhinson, and D. C. Tsui, “Temperature dependence of electron transfer in coupled quantum wells”, Applied Physics Letters, vol. 82, no. 5, pp. 686-688, Feb. 2003.
  12. A. Majumdar, K. K. Choi, J. L. Reno, L. P. Rokhinson, and D. C. Tsui, “Electron transfer based voltage tunable two-color quantum-well infrared photodetectors”, Infrared Physics & Technology, vol. 44, no. 5-6, pp. 337-346, Oct.-Dec. 2003.
  13. A. Majumdar, K. K. Choi, J. L. Reno, and D. C. Tsui, “Voltage tunable two-color infrared detection using semiconductor superlattices”, Applied Physics Letters, vol. 83, no. 25, pp. 5130-5132, Dec. 2003. Selected by Virtual Journal of Nanoscale Science & Technology, vol. 8, no. 26, Dec. 2003. CITATIONS: 20.
  14. A. R. Ellis, A. Majumdar, K. K. Choi, J. L. Reno, and D. C. Tsui, “Binary superlattice quantum-well infrared photodetectors for long-wavelength broadband detection”, Applied Physics Letters, vol. 84, no. 25, pp. 5127-5129, Jun. 2004. Selected by Virtual Journal of Nanoscale Science & Technology, vol. 9, no. 24, Jun. 2004.
  15. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor applications”, IEEE Transactions on Nanotechnology, vol. 4, no. 2, pp. 153-158, Mar. 2005. CITATIONS: 483.
  16. A. Majumdar, A. P. Shah, M. R. Gokhale, S. Sen, S. Ghosh, B. M. Arora, and D. C. Tsui, “High-responsivity high-gain In0.53Ga0.47As/InP quantum-well infrared photodetectors grown using metal-organic vapor phase epitaxy”, IEEE Journal on Quantum Electronics, vol. 41, no. 6, pp. 872-878, Jun. 2005.
  17. A. Majumdar, K. K. Choi, J. L. Reno, and D. C. Tsui, “Voltage tunable superlattice infrared photodetectors for mid- and long-wavelength infrared detection”, Applied Physics Letters, vol. 86, no. 26, art. 261110, Jun. 2005.
  18. R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Application of high-k gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nnotechnology”, Microelectronic Engineering, vol. 80, pp. 1-6, Jun. 2005. CITATIONS: 122.
  19. K. K. Choi, C. Monroy, A. Goldberg, G. Dang, M. Jhabvala, A. La, T. Tamir, K. M. Leung, A. Majumdar, J. Li, and D. C. Tsui, “Designs and applications of corrugated QWIPs”, Infrared Physics & Technology,vol. 47, no. 1-2, pp. 76-90, Oct. 2005.
  20. B. M. Arora, A. Majumdar, A. P. Shah, M. R. Gokhale, S. Ghosh, A. Bhattacharya, and D. Sengupta, “Characteristics of high responsivity 8.5μm InGaAs/InP QWIPs grown by metalorganic vapor phase epitaxy”, Infrared Physics & Technology, vol. 50, no. 2-3, pp. 206-210, Apr. 2007.
  21. A. Majumdar, Z. Ren, J. W. Sleight, D. Dobuzinsky, J. R. Holt, R. Venigalla, S. J. Koester, and W. Haensch, “High-performance, undoped-body, 8-nm-thin SOI field-effect transistors”, IEEE Electron Device Letters, vol. 29, no. 5, pp. 515-517, May 2008. CITATIONS: 29.
  22. O. Gunawan, L. Sekaric, A. Majumdar, M. Rooks, J. Appenzeller, J. W. Sleight, S. Guha, and W. Haensch, “Measurement of carrier mobility in silicon nanowires”, Nano Letters, vol. 8, no. 6, pp. 1566-1571, Jun. 2008. CITATIONS: 82.
  23. S. W. Bedell, A. Majumdar, J. A. Ott, J. Arnold, K. Fogel, S. J. Koester, and D. K. Sadana, “Mobility scaling in short channel length strained Ge-on-insulator P-MOSFETs”, IEEE Electron Device Letters, vol. 29, no. 6, pp. 811-813, Jun. 2008. CITATIONS: 43.
  24. A. Kerber, K. Maitra, A. Majumdar, M. Hargrove, R. J. Carter, and E. Cartier, “Characterization of fast relaxation during BTI stress in conventional and advanced CMOS devices with HfO2/TiN gate stack”, IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3175-3183, Nov. 2008. CITATIONS: 35.
  25. A. Majumdar, X. Wang, A. Kumar, J. R. Holt, D. Dobuzinsky, R. Venigalla, C. Ouyang, S. J. Koester, and W. Haensch, “Gate length and performance scaling of undoped-body, extremely-thin SOI MOSFETs”, IEEE Electron Device Letters, vol. 30, no. 4, pp. 413-415, Apr. 2009. CITATIONS: 27.
  26. L. Sekaric, O. Gunawan, A. Majumdar, X. H. Liu, D. Weinstein, and J. W. Sleight, “Size-dependent modulation of carrier mobility in top-down fabricated silicon nanowires”, Applied Physics Letters, vol. 95, no. 2, art. 023113, Jul. 2009. Selected by Virtual Journal of Nanoscale Science & Technology, vol. 20, no. 4, Jul. 2009. CITATIONS: 15.
  27. A. Majumdar, Z. Ren, S. J. Koester, and W. Haensch, “Undoped-body, extremely-thin SOI MOSFETs with back gates”, IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 2270-2276,Oct. 2009. CITATIONS: 38.
  28. A. Majumdar, I. Lauer, and T. P. O’Regan, “Universality of Zener tunneling in homojunction p-n diodes”, Journal of Applied Physics, vol. 108, no. 2, art. 024501, Jul. 2010.
  29. A. Majumdar, “Experimental determination of wave function spread in Si inversion layers”, Applied Physics Letters, vol. 97, no. 7, art. 072104, Aug. 2010.
  30. S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight, “Universality of short-channel effects in undoped-body silicon nanowire MOSFETs”, IEEE Electron Device Letters, vol. 31, no. 9, pp. 903-905, Sept. 2010. CITATIONS: 20.
  31. A. Majumdar, C. Ouyang, S. J. Koester, and W. Haensch, “Effects of substrate orientation and channel stress on short-channel thin SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 57, no. 9, pp. 2067-2072, Sept. 2010.
  32. A. Majumdar and C.-H. Lin, “Gate capacitance of nanowires with elliptical cross-section”, Applied Physics Letters, vol. 98, no. 7, art. 073506, Feb. 2011.
  33. P. M. Solomon, I. Lauer, A. Majumdar, J. T. Teherani, M. Luisier, J. Cai, and S.J. Koester, “Effect of uniaxial strain on the drain current of an heterojunction tunneling field-effect transistor”, IEEE Electron Device Letters, vol. 32, no. 4, pp. 464-466, Apr. 2011.
  34. Y. Liu, M. Luisier, A. Majumdar, D. A. Antoniadis, and M. S. Lundstrom, “On the interpretation of ballistic injection velocity in deeply scaled MOSFETs”, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 994-1001, Apr. 2012.
  35. A. Majumdar, “Comment on “Zener tunneling in semiconducting nanotubes and grapheme nanoribbon p-n junctions” [Appl. Phys. Lett. 93, 112106 (2008)]”, Applied Physics Letters, vol. 101, no. 25, art. 256103, Dec. 2012.
  36. A. Majumdarand D. A. Antoniadis, “Analysis of carrier transport in short-channel MOSFETs”, IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 351-358, Feb. 2014.
  37. M. Brink, I. Lauer, S. U. Engelmann, A. Majumdar, S. A. Cohen, E. Kratschmer, and M. A. Guillorn, “Contamination mitigation of hydrogen silsesquioxane resist processed with Na+-containing developer for nanoscale CMOS device patterning”, J. Vac. Sci. Techol. B, vol. 32, no. 2, art. 022204, Mar./Apr. 2014.
  38. A. Majumdar, “Semiconductor capacitance penalty per gate in single- and double-gate FETs”, IEEE Electron Device Letters, vol. 35, no. 6, pp. 609-611, Jun. 2014.

 

PUBLICATIONS IN CONFERENCE PROCEEDINGS

  1. A. Majumdar, K. K. Choi, J. L. Reno, L. P. Rokhinson, and D. C. Tsui, “Electron transfer based voltage tunable two-color quantum-well infrared photodetectors,” Proceedings of Photonics 2002: 6th International Conference on Optoelectronics, Fiber Optics, and Photonics, Dec. 2002.
  2. A. P. Shah, M. R. Gokhale, S. Sen, A. Majumdar, S. Ghosh, and B. M. Arora, “InGaAs/InP long wavelength quantum-well infrared photodetectors grown by metal-organic vapor phase epitaxy”, Proceedings of International Workshop on the Physics of Semiconductor Device, vol. 2, pp. 971-973, Dec. 2003.
  3. M. R. Gokhale, A. P. Shah, A. Majumdar, S. Ghosh, S. Sen, and B. M. Arora, “Investigations of InGaAs/InP quantum-well infrared photodetector structures synthesized by MOVPE”, Proceedings of International Conference on Computers and Devices for Communication, Jan. 2004.
  4. S. Datta, J. Brask, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, M. Metz, A. Majumdar, M. Radosavljevic, and R. Chau, “Advanced Si and SiGe strained channel NMOS and PMOS transistors with high-k/metal-gate stack”, Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), vol. 13-14, pp. 194-197, Sept. 2004.
  5. A. Majumdar, K. K. Choi, J. L. Reno, and D. C. Tsui, “Voltage tunable two-color superlattice infrared photodetectors”, Proceedings of SPIE, vol. 5543, pp. 92-97, Nov. 2004.
  6. R. Chau, M. Doczy, B. Doyle, S. Datta, G. Dewey, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications”, Proceedings of International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp. 26-30, Oct. 2004. CITATIONS: 17.
  7. R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Emerging silicon and non-silicon nanoelectronic devices: Opportunities and challenges for future high-performance and low-power computational applications”, Proceedings of International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 13-16, Apr. 2005.
  8. R. Chau, S. Datta, and A. Majumdar, “Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications”, Compound Semiconductor Integrated Circuit Symposium (CSICS) Technical Digest, pp. 17-20, Oct. 2005. CITATIONS: 70.
  9. J. Cai, A. Majumdar, D. Dobuzinsky, T. H. Ning, S. J. Koester, and W. E. Haensch, “Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond”, IEDM Technical Digest, pp. 907-910, Dec. 2007.
  10. K. L. Saenger, S. W. Bedell, M. Copel, A. Majumdar, J. A. Ott, J. P. de Souza, S. J. Koester, D. R. Wall, and D. K. Sadana, “Effect of elevated implant temperature on amorphization and activation in As-implanted silicon-on-insulator layers”, Materials Research Society Symposium Proceedings, vol. 1070, paper 1070-E05-02, Mar. 2008.
  11. S. W. Bedell, A. Majumdar, K. Jenkins, J. A. Ott, J. Arnold, K. Fogel, S. J. Koester, and D. K. Sadana, “DC and RF characterization of sub-100-nm-gate-length strained Ge-on-insulator P-MOSFETs”, Device Research Conference Digest, pp. 45-46, Jun. 2008.
  12. O. Gunawan, L. Sekaric, A. Majumdar, M. Rooks, J. Appenzeller, J. W. Sleight, S. Guha, and W. Haensch, “Measurement of carrier mobility in silicon nanowires”, Device Research Conference Digest, pp. 189-190, Jun. 2008.
  13. J. Cai, Z. Ren, A. Majumdar, T. H. Ning, H. Yin, D. G. Park, and W. E. Haensch, “Will SOI have a life for the low-power market ?”, IEEE International SOI Conference Digest, pp. 15-16, Oct. 2008.
  14. C. Wang, J. Chang, C. H. Lin, A. Kumar, A. Gehring, J. Cho, A. Majumdar, A. Bryant, Z. Ren, K. Chan, T. Kanarsky, X. Wang, O. Dokumaci, M. Guillorn, M. Khater, Q. Yang, X. Li, M. Naeem, J. Holt, Y. Moon, J. King, J. Yates, Y. Zhang, D. G. Park, C. Ouyang, and W. Haensch, “FinFET resistance mitigation through design and process optimization”, Proceedings of International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 127-128, Apr. 2009.
  15. J. Y. Li, J. C. Sturm, A. Majumdar, I. Lauer, and S. J. Koester, “Bandgap dependence of band-to-band tunneling and defect-mediated excess currents in SiGe/Si heterojunction tunnel diodes grown by RTCVD”, Device Research Conference Digest, pp. 99-100, Jun. 2009.
  16. S. Bangsaruntip, G. M. Cohen, A. Majumdar, Y. Zhang, S. U. Engelmann, N. C. M. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. Guillorn, T. Barwicz, L. Sekaric, M. M. Frank, and J. W. Sleight, “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling”, IEDM Technical Digest, pp. 297-300, Dec. 2009. CITATIONS: 122.
  17. J. W. Sleight, S. Bangsaruntip, G. Cohen, A. Majumdar, Y. Zhang, S. Engelmann, N. Fuller, L. Gignac, S. Mittal, J. Newbury, T. Barwicz, M. Frank, and M. Guillorn, “High performance and highly uniform metal high-K gate-all-around silicon nanowire MOSFETs”, ECS Transactions, vol. 28, no. 1, pp. 179-189, Apr. 2010.
  18. A. Khakifirooz, K. Cheng, P. Kulkarni, J. Cai, S. Ponoth, J. Kuss, B. S. Haran, A. Kimball, L. F. Edge, A. Reznicek, T. Adam, H. He, N. Loubet, S. Mehta, S. Kanakasabapathy, S. Schmitz, S. Holmes, B. Jagannathan, A. Majumdar, D. Yang, A. Upham, S. C. Seo, J. L. Herman, R. Johnson, Y. Zhu, P. Jamison, Z. Zhu, L. H. Vanamurth, J. Faltermeier, S. Fan, D. Horak, H. Bu, D. K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris, W. Haensch, E. Leobondung, and G. Shahidi, “Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications”, Proceedings of International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 110-111, Apr. 2010.
  19. S. Bangsaruntip, A. Majumdar, G. M. Cohen, S. U. Engelmann, Y. Zhang, M. Guillorn, L. M. Gignac, S. Mittal, W. S. Graham, E. A. Joseph, D. P. Klaus, J. Chang, E. A. Cartier, and J. W. Sleight, “Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm”, Symposium on VLSI Technology Digest of Technical Papers, pp. 21-22, Jun. 2010. CITATIONS: 62.
  20. J. W. Sleight, S. Bangsaruntip, A. Majumdar, G. M. Cohen, Y. Zhang, S. U. Engelmann, N. C. M. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. M. Frank, J. Chang, and M. Guillorn, “Gate-all-around silicon nanowire MOSFETs and circuits”, Device Research Conference Digest, pp. 269-272, Jun. 2010.
  21. G. M. Cohen, E. Cartier, S. Bangsaruntip, A. Majumdar, W. Haensch, L. M. Gignac, S. Mittal, and J. W. Sleight, “Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter”, Device Research Conference Digest, pp. 277-278, Jun. 2010.
  22. S. J. Koester, I. Lauer, A. Majumdar, J. Cai, J. Sleight, S. Bedell, P. Solomon, S. Laux, L. Chang, S. Koswatta, W. Haensch, P. Tomasini, and S. Thomas, “Are Si/SiGe tunneling field-effect transistors a good idea ?”, ECS Transactions, vol. 33, no. 6, pp. 357-361, Oct. 2010.
  23. M. A. Guillorn, J. Chang, A. Pyzyna, S. Engelmann, M. Glodde, E. Joseph, R. Bruce, J. A. Ott, A. Majumdar, F. Liu, M. Brink, S. Bangsaruntip, M. Khater, S. Mauer, I. Lauer, C. Lavoie, Z. Zhang, J. Newbury, E. Kratschmer, D. P. Klaus, J. Bucchignano, B. To, W. Graham, E. Sikorski, V. Narayanan, N. Fuller, and W. Haensch, “A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch”, Symposium on VLSI Technology Digest of Technical Papers, pp. 64-65, Jun. 2011.
  24. A. Majumdar and D. A. Antoniadis, “Possible observation of ballistic contact resistance in wide Si MOSFETs”, Device Research Conference Digest, pp. 197-198, Jun. 2012.
  25. A. Majumdar, S. Bangsaruntip, G. M. Cohen, L. M. Gignac, M. Guillorn, M. M. Frank, J. W. Sleight, and D. A. Antoniadis, “Room-temperature carrier transport in high-performance short-channel silicon nanowire MOSFETs”, IEDM Technical Digest, pp. 179-182, Dec. 2012.
  26. P. Hashemi, M. Kobayashi, A. Majumdar, L. A. Yang, A. Baraskar, K. Balakrishnan, W. Kim, K. Chan, S. U. Engelmann, J. A. Ott, S. W. Bedell, C. E. Murray, S. Liang, R. H. Dennard, J. W. Sleight, E. Leobandung, and D. G. Park, “High-performance Si1-xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions”, Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19, Jun. 2013.
  27. Y. Sun, A. Majumdar, C.-W. Cheng, Y.-H. Kim, U. Rana, R. M. Martin, R. L. Bruce, K.-T. Shiu, Y. Zhu, D. Farmer, M. Hopstaken, E. A. Joseph, J. P. de Souza, M. M. Frank, S.-L. Cheng, M. Kobayashi, D. K. Sadana, D.-G. Park, and E. Leobandung, “Self-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution”, IEDM Technical Digest, pp. 48-51, Dec. 2013.
  28. S. Bangsaruntip, K. Balakrishnan, S.-L. Cheng, J. Chang, M. Brink, I. Lauer, L. M. Gignac, R. L. Bruce, S. U. Engelmann, A. Pyzyna, G. M. Cohen, C. Breslin, J. S. Newbury, D. Klaus, A. Majumdar, J. W. Sleight, and M. A. Guillorn, “Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond”, IEDM Technical Digest, pp. 526-529, Dec. 2013.
  29. P. Hashemi, K. Balakrishnan, A. Majumdar, A. Khakifirooz, W. Kim, A. Baraskar, L. Yang, K. Chan, S. U. Engelmann, J. A. Ott, D. A. Antoniadis, E. Leobandung, and D-G. Park, “Strained Si1-xGex-on-insulator trigate PMOSFETs with excellent sub-threshold leakage and extremely-high short channel performance, source injection velocity and transconductance at VDD down to 0.5V”, Symposium on VLSI Technology Digest of Technical Papers, pp. 16-17, Jun. 2014.