Phillip J Restle  Phillip J Restle photo         

contact information

Distinguished-RSM: Clocking & Power-Noise Mitigation for IBM Systems
Thomas J. Watson Research Center, Yorktown Heights, NY USA


Professional Associations

Professional Associations:  IBM Academy of Technology  |  IEEE, Senior Member


IBM zSeries z6 (65nm SOI Technology) Global Clock Distribution for >4.5GHz Cores:

Visualizing voltages and currents (or delay) of wires and circuits from IBM-internal global clock simulation and tuning tools.

This shows start-up of "L0 tree" cross-section of the global clock distribution from PLL to a subset sector buffers in bottom 3rd of chip

[See the previous page Key to Clock Network Visualizations for more detailed description of what is being shown, and what the different colors and shapes mean.]

Short description: In the following animation Z axis is Voltage, diameter and color is Current of buffer or wire.
Transmission-line models are used with freq. dep. L(f) and R(f) synthesized from AQUAIA runs.




POWER6 Global Clock Distribution for >5GHz Cores:

Also IBM 65nm SOI technoloy.  All of L0 tree to both cores shown, but only 6 sectors of L1 tree (front right corner).
(Reload to re-start animation from PLL to clock grid)


This next version shows continuous steady state at 5 GHz (after ~2 cycle start-up)


This next static image shows delay of global clock to both cores

Some Acknowledgements for above work:

Nicole Schwartz - Clock distribution developer and designer extraordinaire
Michael Thomson - Clocktree tool developer and wire model expert
Steve Walker - General methodology guru and simulation infrastructure leader
Scott Neely - Partner in generating excessively cool VLSI-design visualizations
Izzy Bendrihem - CTE (Common Tools Environment) Authority
Josh Friedrich - POWER6 timing and product frequency lead

Visualizations generated using versions of open-source visualization tools: and