Stas Polonsky, Keith A. Jenkins, et al.
IEEE ITC 2004
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Stas Polonsky, Keith A. Jenkins, et al.
IEEE ITC 2004
Joachim N. Burghartz, Andrew C. Megdanis, et al.
IEEE Electron Device Letters
Sandip Tiwari, Farhan Rana, et al.
Applied Physics Letters
Phillip J. Restle, Craig A. Carter, et al.
ISSCC 2002