Conference paper
A SiGe-base PNP ECL circuit technology
D.L. Harame, J.H. Comfort, et al.
VLSI Technology 1993
The Letter describes the first experimental result of a high-speed low-power ECL-based AC-coupled complementary push-pull circuit. Implemented in a 0.8µm high-performance fully complementary bipolar technology with 50GHz npn transistor and 13GHz pnp transistor, a power-delay product of 34fJ (23.2ps at 1.48mW) has been achieved compared with 67 fJ (45 ps at 1.48mW) for the npn-only ECL circuit. © 1993, The Institution of Electrical Engineers. All rights reserved.
D.L. Harame, J.H. Comfort, et al.
VLSI Technology 1993
R. Puri, C.T. Chuang
VLSID 2000
Christophe R. Tretz, C.T. Chuang, et al.
International Journal of Electronics
J.N. Burghartz, J.H. Comfort, et al.
IEDM 1990