K.A. Chao
Physical Review B
A cost effective 28 nm CMOS Interconnect technology is presented for 28 nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization using conventional tools and processes. High yields and robust reliability were demonstrated. © 2011 Elsevier B.V. All rights reserved.
K.A. Chao
Physical Review B
Imran Nasim, Melanie Weber
SCML 2024
Sharee J. McNab, Richard J. Blaikie
Materials Research Society Symposium - Proceedings
A.B. McLean, R.H. Williams
Journal of Physics C: Solid State Physics